IS61NLP102418-250B3 ISSI, Integrated Silicon Solution Inc, IS61NLP102418-250B3 Datasheet - Page 25

• Manufacturer Part Number: IS61NLP102418-250B3
• Description: IC SRAM 18MBIT 250MHZ 165FBGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61NLP102418-250B3

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (1M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
INSTRUCTION CODES
TAP CONTROLLER STATE DIAgRAM
Integrated Silicon Solution, Inc. — www.issi.com
Rev. M
01/06/2011
Code
000
001
010
011
100
101
110
111
SAMPLE/PRELOAD
RESERVED
RESERVED
RESERVED
Instruction
SAMPLE-Z
EXTEST
IDCODE
BYPASS
1
0
Test Logic Reset
Run Test/Idle
0
Description
Captures the Input/Output ring contents. Places the boundary scan register be-
tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
1
1
0
1
Capture DR
Update DR
Select DR
Pause DR
Exit1 DR
Exit2 DR
Shift DR
0
1
1
1
0
0
0
0
0
1
1
1
0
1
Capture IR
Update IR
Select IR
Pause IR
Exit1 IR
Exit2 IR
Shift IR
0
1
1
0
1
0
0
0
0
1
1
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