MT48LC64M8A2P-75 IT:C TR Micron Technology Inc, MT48LC64M8A2P-75 IT:C TR Datasheet - Page 29
![IC SDRAM 512MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC64M8A2P-75 IT:C TR
Manufacturer Part Number
MT48LC64M8A2P-75 IT:C TR
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75 IT:C TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 18:
Figure 19:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
WRITE Burst
WRITE-to-WRITE
Note:
Note:
COMMAND
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 21 on page 30. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
COMMAND
ADDRESS
ADDRESS
BL = 2. DQM is LOW.
DQM is LOW. Each WRITE command may be to any bank.
CLK
CLK
DQ
DQ
Transitioning Data
WRITE
WRITE
BANK,
COL n
BANK,
COL n
D
T0
D
T0
n
IN
n
IN
Transitioning Data
n + 1
NOP
n + 1
NOP
D
T1
T1
D
IN
IN
29
Don’t Care
WRITE
BANK,
COL b
NOP
T2
T2
D
b
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Don’t Care
T3
NOP
512Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
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