MT48LC64M8A2P-75 IT:C TR Micron Technology Inc, MT48LC64M8A2P-75 IT:C TR Datasheet - Page 61
![IC SDRAM 512MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC64M8A2P-75 IT:C TR
Manufacturer Part Number
MT48LC64M8A2P-75 IT:C TR
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75 IT:C TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 45:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
COMMAND
BA0, BA1
A11, A12
A0–A9,
DQM/
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
WRITE – Without Auto Precharge
t CKH
t CMH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
NOP
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <D
3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
DISABLE AUTO PRECHARGE
quency.
t CMS
t CL
t DS
COLUMN m 2
WRITE
BANK
T2
D
IN
t CMH
t CH
t DH
m
t DS
D
IN
T3
NOP
m + 1
t DH
t DS
D
IN
T4
NOP
m + 2
t DH
61
t DS
D
IN
IN
T5
NOP
m + 3
m> and the PRECHARGE command, regardless of fre-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t
WR
T6
NOP
3
512Mb: x4, x8, x16 SDRAM
PRECHARGE
SINGLE BANK
ALL BANKs
T7
BANK
©2000 Micron Technology, Inc. All rights reserved.
Timing Diagrams
t RP
NOP
T8
ACTIVE
ROW
ROW
BANK
T9
Don’t Care
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