M25P05-AVMN6TP NUMONYX, M25P05-AVMN6TP Datasheet - Page 10

• Manufacturer Part Number: M25P05-AVMN6TP
• Description: IC FLASH 512KBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SO N
• Cell Type: NOR
• Density: 512 Kb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 256
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P05-AVM6TPTR; M25P05-AVMN6TP; M25P05-AVMN6TPTR

SPI modes
3
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SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in standby mode and not transferring data:
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in
that the M25P05-A is not selected if the bus master leaves the S line in the high impedance
state. As the bus master may enter a state where all inputs/outputs are in high impedance at
the same time (for example, when the bus master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the t
typical value of R is 100 kΩ, assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the bus master leaves the
SPI bus in high impedance.
SPI interface with
(CPOL, CPHA) =
CS3
SPI bus master
(0, 0) or (1, 1)
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CS2 CS1
shows an example of three devices connected to an MCU, on an SPI bus. Only one
Bus master and memory devices on the SPI bus
SDO
SDI
SCK
R
R
C Q D
S
SPI memory
device
W
V
CC
HOLD
V
R
SS
C Q D
S
Figure
SPI memory
device
SHCH
W
4, is the clock polarity when the
V
HOLD
CC
requirement is met). The
p
R
V
(C
SS
p
= parasitic
C Q D
Figure
S
SPI memory
device
3) ensure
W
M25P05-A
V
CC
HOLD
AI12836b
V
SS
V
V
SS
CC