M25P05-AVMN6TP NUMONYX, M25P05-AVMN6TP Datasheet - Page 12

• Manufacturer Part Number: M25P05-AVMN6TP
• Description: IC FLASH 512KBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SO N
• Cell Type: NOR
• Density: 512 Kb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 256
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P05-AVM6TPTR; M25P05-AVMN6TP; M25P05-AVMN6TPTR

Operating features
4
4.1
4.2
4.3
4.4
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Operating features
Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one
byte, and a page program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal program cycle (of duration t
To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see
program (PP)
Sector erase and bulk erase
The page program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the sector erase (SE) instruction, or throughout the
entire memory, using the bulk erase (BE) instruction. This starts an internal erase cycle (of
duration t
The erase instruction must be preceded by a write enable (WREN) instruction.
Polling during a write, program or erase cycle
A further improvement in the time to write status register (WRSR), program (PP) or erase
(SE or BE) can be achieved by not waiting for the worst case delay (t
write in progress (WIP) bit is provided in the status register so that the application program
can monitor its value, polling it to establish when the previous write cycle, program cycle or
erase cycle is complete.
Active power, standby power and deep power-down modes
When Chip Select (S) is Low, the device is selected, and in the active power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the active power
mode until all internal cycles have completed (program, erase, write status register). The
device then goes in to the standby power mode. The device consumption drops to I
The deep power-down mode is entered when the specific instruction (the deep power-down
(DP) instruction) is executed. The device consumption drops further to I
remains in this mode until another specific instruction (the release from deep power-down
and read electronic signature (RES) instruction) is executed.
While in the deep power-down mode, the device ignores all write, program and erase
instructions (see
software protection mechanism, when the device is not in active use, to protect the device
from inadvertent write, program or erase instructions.
SE
or t
and
BE
Section 6.11: Deep power-down
).
Table 14: Instruction
times).
(DP)). This can be used as an extra
PP
).
W
Section 6.8: Page
, t
CC2
PP
, t
. The device
SE
, or t
M25P05-A
BE
CC1
). The
.