M25P05-AVMN6TP NUMONYX, M25P05-AVMN6TP Datasheet - Page 13
M25P05-AVMN6TP
Manufacturer Part Number
M25P05-AVMN6TP
Description
IC FLASH 512KBIT 50MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P05-AVMN6P.pdf
(52 pages)
Specifications of M25P05-AVMN6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
512K (64K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Package
8SO N
Cell Type
NOR
Density
512 Kb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
256Byte x 256
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P05-AVM6TPTR
M25P05-AVMN6TP
M25P05-AVMN6TPTR
M25P05-AVMN6TP
M25P05-AVMN6TPTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P05-AVMN6TP
Manufacturer:
FREESCALE
Quantity:
110
Company:
Part Number:
M25P05-AVMN6TP
Manufacturer:
NUMONYX
Quantity:
2 350
Part Number:
M25P05-AVMN6TP
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ST
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Company:
Part Number:
M25P05-AVMN6TP(25P05VP)
Manufacturer:
TI
Quantity:
13
M25P05-A
4.5
4.5.1
4.5.2
4.5.3
4.5.4
Status register
The status register contains a number of status and control bits, as shown in
can be read or set (as appropriate) by specific instructions.
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write status
register, program or erase cycle.
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch.
BP1, BP0 bits
The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against program and erase instructions.
SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal
allow the device to be put in the hardware protected mode. In this mode, the non-volatile bits
of the status register (SRWD, BP1, BP0) become read-only bits.
Operating features
Table
6, that
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