M25P05-AVMN6TP NUMONYX, M25P05-AVMN6TP Datasheet - Page 35

• Manufacturer Part Number: M25P05-AVMN6TP
• Description: IC FLASH 512KBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SO N
• Cell Type: NOR
• Density: 512 Kb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 256
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P05-AVM6TPTR; M25P05-AVMN6TP; M25P05-AVMN6TPTR

M25P05-A
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V
power on reset (POR) threshold voltage, V
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page program (PP), sector erase
(SE), bulk erase (BE) and write status register (WRSR) instructions until a time delay of
t
correct operation of the device is not guaranteed if, by this time, V
No write status register, program or erase instructions should be sent until the later of:
These values are specified in
If the delay, t
selected for read instructions even if the t
At power-up, the device is in the following state:
Normal precautions must be taken for supply rail decoupling, to stabilize the V
Each device in a system should have the V
the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when V
(POR) threshold voltage, V
to any instruction (the designer needs to be aware that if a power-down occurs while a write,
program or erase cycle is in progress, some data corruption can result).
PUW
V
V
t
t
The device is in the standby mode (not the deep power-down mode)
The write enable latch (WEL) bit is reset
The write in progress (WIP) bit is reset.
has elapsed after the moment that V
PUW
VSL
CC
SS
(min) at power-up, and then for a further delay of t
at power-down
after V
after V
VSL
, has elapsed, after V
CC
CC
passed the V
passed the V
CC
WI
drops from the operating voltage, to below the power on reset
, all operations are disabled and the device does not respond
Table 8.
CC
CC
) until V
WI
Section 3: SPI
(min) level
threshold
CC
has risen above V
CC
PUW
CC
WI
CC
reaches the correct value:
– all operations are disabled, and the device
rises above the V
rail decoupled by a suitable capacitor close to
delay is not yet fully elapsed.
modes.
VSL
CC
(min), the device can be
Power-up and power-down
WI
CC
threshold. However, the
is still below V
CC
is less than the
CC
supply.
CC
(min).
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