M25P05-AVMN6TP NUMONYX, M25P05-AVMN6TP Datasheet - Page 22

• Manufacturer Part Number: M25P05-AVMN6TP
• Description: IC FLASH 512KBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SO N
• Cell Type: NOR
• Density: 512 Kb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 256
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P05-AVM6TPTR; M25P05-AVMN6TP; M25P05-AVMN6TPTR

Instructions
6.4
6.4.1
6.4.2
6.4.3
6.4.4
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Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status
register may be read at any time, even while a program, erase or write status register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
write in progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the status register continuously, as shown in
Table 6.
The status and control bits of the status register are as follows:
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write status
register, program or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to
‘0’ no such cycle is in progress.
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When
set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is
reset and no write status register, program or erase instruction is accepted.
BP1, BP0 bits
The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against program and erase instructions. These bits are written with the
write status register (WRSR) instruction. When one or both of the block protect (BP1, BP0)
bits is set to ‘1’, the relevant memory area (as defined in
against page program (PP) and sector erase (SE) instructions. The block protect (BP1,
BP0) bits can be written provided that the hardware protected mode has not been set. The
bulk erase (BE) instruction is executed if, and only if, both block protect (BP1, BP0) bits are
0.
SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The status register write disable (SRWD) bit and write protect (W) signal
allow the device to be put in the hardware protected mode (when the status register write
disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In this mode, the non-
volatile bits of the status register (SRWD, BP1, BP0) become read-only bits and the write
status register (WRSR) instruction is no longer accepted for execution.
Status register write protect
SRWD
b7
Status register format
0
0
0
BP1
Figure
Block protect bits
Table
10.
Write enable latch bit
BP0
2) becomes protected
WEL
Write in progress bit
M25P05-A
WIP
b0