M28W160ECB70ZB6E NUMONYX, M28W160ECB70ZB6E Datasheet - Page 11

• Manufacturer Part Number: M28W160ECB70ZB6E
• Description: IC FLASH 16MBIT 70NS 46TFBGA
• Manufacturer: NUMONYX

Specifications of M28W160ECB70ZB6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 46-TFBGA
• Package: 46TFBGA
• Cell Type: NOR
• Density: 16 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 31
• Timing Type: Asynchronous
• Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time during, to
monitor the progress of the operation, or the Pro-
gram/Erase states. See
Write State Machine Current/Next, for a summary
of the Command Interface.
The Command Interface is reset to Read mode
when power is first applied, when exiting from Re-
set or whenever V
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to
in conjunction with the text descriptions below.
Read Memory Array Command
The Read command returns the memory to its
Read mode. One Bus Write cycle is required to is-
sue the Read Memory Array command and return
the memory to Read mode. Subsequent read op-
erations will read the addressed location and out-
put the data. When a device Reset occurs, the
memory defaults to Read mode.
Read Status Register Command
The Status Register indicates when a program or
erase operation is complete and the success or
failure of the operation itself. Issue a Read Status
Register command to read the Status Register’s
contents. Subsequent Bus Read operations read
the Status Register at any address, until another
command is issued. See
ter
The Read Status Register command may be is-
sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con-
tent of the Status Register.
Read Electronic Signature Command
The Read Electronic Signature command reads
the Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status, or the Protec-
tion and Lock Register. See Tables 4,
the valid address.
Read CFI Query Command
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area, allowing programming equipment or appli-
Bits, for details on the definitions of the bits.
DD
is lower than V
APPENDIX
Table 10., Status Regis-
Table 3.,
D.,
Commands,
5
LKO
Table
and
. Com-
6
31.,
for
cations to automatically match their interface to
the characteristics of the device. One Bus Write
cycle is required to issue the Read Query Com-
mand. Once the command is issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See
B., COMMON FLASH INTERFACE
25, 26, 27, 28,
mation contained in the Common Flash Interface
memory area.
Block Erase Command
The Block Erase command can be used to erase
a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error.
Two Bus Write cycles are required to issue the
command.
■
■
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.
Erase aborts if Reset turns to V
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Register command and the Pro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in
gram/Erase Endurance
See
and Pseudo
using the Erase command.
Program Command
The memory array can be programmed word-by-
word. Two bus write cycles are required to issue
the Program Command.
■
■
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are given in
Times and Program/Erase Endurance
The first bus cycle sets up the Erase
command.
The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
The first bus cycle sets up the Program
command.
The second latches the Address and the Data
to be written and starts the Program/Erase
Controller.
APPENDIX
Table 7., Program, Erase Times and Pro-
Code, for a suggested flowchart for
M28W160ECT, M28W160ECB
29
C.,
and
Figure 20., Erase Flowchart
30
Cycles.
Table 7., Program, Erase
for details on the infor-
IL
. As data integrity
(CFI), Tables
APPENDIX
Cycles.
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