M28W160ECB70ZB6E NUMONYX, M28W160ECB70ZB6E Datasheet - Page 38

• Manufacturer Part Number: M28W160ECB70ZB6E
• Description: IC FLASH 16MBIT 70NS 46TFBGA
• Manufacturer: NUMONYX

Specifications of M28W160ECB70ZB6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 46-TFBGA
• Package: 46TFBGA
• Cell Type: NOR
• Density: 16 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 31
• Timing Type: Asynchronous
• Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M28W160ECT, M28W160ECB
Table 29. Primary Algorithm-Specific Extended Query Table
Note: 1. See
38/50
(P+10)h = 45h
(P+11)h = 46h
(P+12)h = 47h
(P+13)h = 48h
(P+7)h = 3Ch
(P+8)h = 3Dh
(P+A)h = 3Fh
(P+C)h = 41h
(P+D)h = 42h
(P+0)h = 35h
(P+1)h = 36h
(P+2)h = 37h
(P+3)h = 38h
(P+4)h = 39h
(P+5)h = 3Ah
(P+6)h = 3Bh
(P+9)h = 3Eh
(P+B)h = 40h
(P+E)h = 43h
(P+F)h = 44h
P = 35h
Offset
(1)
Table
26., offset 15 for P pointer definition.
00C0h
0050h
0052h
0049h
0031h
0030h
0066h
0000h
0000h
0000h
0001h
0003h
0000h
0030h
0001h
0080h
0000h
0003h
0003h
Data
Primary Algorithm extended Query table unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation
Block Lock Status
Defines which bits in the Block Status Register section of the Query are
implemented.
Address (P+A)h contains less significant byte
V
V
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
Protection Field 1: Protection Description
This field describes user-available. One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-programmable.
Reserved
DD
PP
bit 0Chip Erase supported(1 = Yes, 0 = No)
bit 1Suspend Erase supported(1 = Yes, 0 = No)
bit 2Suspend Program supported(1 = Yes, 0 = No)
bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No)
bit 4Queued Erase supported(1 = Yes, 0 = No)
bit 5Instant individual block locking supported(1 = Yes, 0 = No)
bit 6Protection bits supported(1 = Yes, 0 = No)
bit 7Page mode read supported(1 = Yes, 0 = No)
bit 8Synchronous read supported(1 = Yes, 0 = No)
bit 31 to 9Reserved; undefined bits are ‘0’
bit 0Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1Reserved; undefined bits are ‘0’
bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)
bit 1Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)
bit 15 to 2Reserved for future use; undefined bits are ‘0’
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
bit 0 to 7 Lock/bytes JEDEC-plane physical low address
bit 8 to 15Lock/bytes JEDEC-plane physical high address
bit 16 to 23 "n" such that 2
bit 24 to 31 "n" such that 2
Supply Optimum Program/Erase voltage
Logic Supply Optimum Program/Erase voltage (highest performance)
n
n
= factory pre-programmed bytes
= user programmable bytes
Description
8 Byte
8 Byte
Value
12V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
80h
00h
"P"
"R"
"1"
"0"
No
No
No
No
No
3V
01
"I"