RC28F128M29EWLA NUMONYX, RC28F128M29EWLA Datasheet - Page 15

• Manufacturer Part Number: RC28F128M29EWLA
• Description: IC FLASH 128MBIT 25NS 64BGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of RC28F128M29EWLA

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 60ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Numonyx
2
2.1
2.2
2.3
2.4
2.5
2.6
®
Axcell™ M29EW
Signal Descriptions
See
signals.
Address inputs (A0-A22)
The Address inputs select the cells in the memory array, CFI space to access during Bus
Read operations. During Bus Write operations they direct the commands sent to the
command interface of the Program/Erase controller.
Data inputs/outputs (DQ0-DQ7)
During Bus Read operations, the data lines output the data stored at the selected address or
register. During Bus Write operations, the data lines are used to input data or commands.
Data inputs/outputs (DQ8-DQ14)
During Bus Read operations, the data lines output the data stored at the selected address
when BYTE# is High, V
impedance. During Bus Write operations the Command Register does not use these bits.
Ignore these bits when reading the Status Register .
Data input/output or address input (DQ15/A 1)
When the device operates in x16 bus mode, this pin behaves as a Data input/output pin,
together with DQ8-DQ14. When the device operates in x8 bus mode, this pin behaves as
the least significant bit of the address. Throughout this document, when both references
occur, consider the DQ15 function adding to the other data lines when in X16 mode and the
A-1 function adding to the others addresses when in X8 mode, except when explicitly stated
otherwise.
Chip Enable (CE#)
The Chip Enable pin, CE#, activates the memory when it’s low, V
Bus Write operations to be performed. When Chip Enable is High, V
deselected and power is reduced to standby level.
Output Enable (OE#)
The Output Enable pin, OE#, controls the Bus Read operation of the memory.
Figure 1: Logic
diagram, and
IH
. When BYTE# is Low, V
Table 1: Signal
208031-04
descriptions, for a brief overview of device
IL
, these pins are not used and are high
IL
, allowing Bus Read and
IH
, the memory is
Signal Descriptions
15