IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet - Page 14
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IDT7130SA55P
Manufacturer Part Number
IDT7130SA55P
Description
IC SRAM 8KBIT 55NS 48DIP
Manufacturer
IDT, Integrated Device Technology Inc
Series
-r
Specifications of IDT7130SA55P
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-DIP
Density
8Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
20b
Package Type
PDIP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
155mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
48
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
7130SA55P
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT7130SA55P
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT7130SA55PF
Manufacturer:
HIROSE ELECTRIC
Quantity:
4
Company:
Part Number:
IDT7130SA55PF
Manufacturer:
IDT
Quantity:
300
Company:
Part Number:
IDT7130SA55PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT7130SA55PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Timing Waveform of BUSY Arbitration Controlled by CE Timing
Timing Waveform by BUSY Arbitration Controlled
by Address Match Timing
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
NOTES:
1. PLCC, TQFP and STQFP package only.
2. 'X' in part numbers indicates power rating (SA or LA).
ADDR
ADDR
BUSY
'A'
INTERRUPT TIMING
t
t
t
t
AS
WR
INS
INR
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
BUSY
AND
ADDR
Symbol
APS
CE
CE
'A'
'B'
'B'
is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).
'B'
'A'
'B'
'A'
Interrupt Set Time
Interrupt Reset Time
Address Set-up Time
Write Recovery Time
t
APS
(2)
t
APS
(2)
ADDRESSES MATCH
Parameter
t
BAA
t
RC
t
BAC
OR t
(1)
WC
ADDRESSES MATCH
14
Min.
____
____
0
0
Com'l Only
7130X20
7140X20
Military, Industrial and Commercial Temperature Ranges
t
BDC
ADDRESSES DO NOT MATCH
Max.
(1)
(1)
____
____
20
20
t
BDA
Min.
____
____
(2)
0
0
Com'l, Ind
& Military
7130X25
7140X25
Max.
____
____
25
25
Min.
____
____
0
0
& Military
7130X35
7140X35
Com'l
(1)
Max.
____
____
25
25
2689 drw 14
2689 drw 15
2689 tbl 12a
Unit
ns
ns
ns
ns