IDT70824S35PF8 IDT, Integrated Device Technology Inc, IDT70824S35PF8 Datasheet - Page 3

• Manufacturer Part Number: IDT70824S35PF8
• Description: IC SARAM 64KBIT 35NS 80TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70824S35PF8

• Format - Memory: RAM
• Memory Type: SARAM
• Memory Size: 64K (4K x 16)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70824S35PF8

Pin Descriptions: Sequential Access Port
Pin Descriptions: Random Access Port
NOTE:
1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
I/O
R/W
GND
SYMBOL
SI/O0-15
SCLK
SR/W
A
CE
CMD
OE
LB, UB
V
SCE
CNTEN
SLD
SSTRT
SSTRT
EOB
EOB
SOE
RST
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
0
CC
-A
SYMBOL
0
-I/O
11
1
2
,
15
1
2
,
Inputs/Outputs
Chip Enable
Control Register Enable
Read/Write Enable
Output Enable
Lower Byte, Upper Byte
Enables
Power Supply
Ground
NAME
Inputs/Outputs
Clock
Chip Enable
Counter Enable
Read/Write Enable
Load Start of Address
Register
End of Buffer Flag
Output Enable
Reset
Address Lines
Address Pointer Load Control
NAME
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Random access data inputs/outputs for 16-Bit wide data.
into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE =
control register, the flag register and the start and end of buffer registers. CMD and CE may not be LOW at the
same time.
If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when
R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and
stated and blocked during read and write operations. UB controls access for I/O
is asynchronous
Seven +5 power supply pins. All V
DESCRIPTION
Sequential data inputs/outputs for 16-bit wide data.
SI/O
access port address pointer increments by 1 on e ach LOW-TO-HIGH transition of SCLK when CNTEN is LOW.
is HIGH, the sequential access port is disabled into powered-d own mode on the LOW-to-HIGH transition of
SCLK, and the SI/O outputs are in the High-impedance state. All data is retained , unless altered by the random
access port.
independent of CE.
HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination
o f a write cycle is done on the LOW-to -HIGH transition of SCLK if SR/W or SCE is HIGH.
SCLK. On the Cycle following SLD, the address pointer charges to the address location contained in the data-
in register. SSTRT
may not be LOW while SLD is LOW or during the cycle following SLD.
of buffer registers. The flags can be cleared by either asserting RST LOW or by writing ze ro into Bit 0 and/or
Bit 1 of the control registe r at address 101. EOB
se quentially ad dressed data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state.
Address inputs to access the 4096-word (16-Bit) memory array.
When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled
V
When CMD is LOW, address lines A
CMD may not be LOW at the same time.
When OE is LOW and R/W is HIGH, I/O
the High-impedance state.
When LB is LOW, I/O
from LB.
Ten ground pins. All ground pins must be connected to the same ground supply.
When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transitio n of SCLK. When SCE
When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is
When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/ W is
When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When
SLD is LOW, data on the inputs SI/O
When SSTRT
the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT
EOB
therefore separate match addresses.
SOE controls the data outputs and is independe nt of SCLK. When SOE is LOW, output buffers and the
SOE is asynchronous to SCLK.
When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the
EOB
IH
, unless it is altered by the sequential port CE and CMD may not be LOW at the same time.
0
1
1
-SI/O
or EOB
and EOB
15
,SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential
1
2
2
or SSTRT
is output low when the address pointer is incremented to match the address stored in the end
flags are set HIGH. RST is asynchronous to SCLK.
1
and SSTRT
0
-I/O
2
6.42
7
is LOW, the start of address register #1 or #2 is load ed into the address pointer on
3
are accessible for read and write operations. When LB is HIGH, I/O
2
(1)
may not be LOW while SLD is LOW or during the cycle following SLD.
CC
0
0
-A
-SI/O
(1)
pins must be connected to the same +5V V
2
0
, R/W, and inputs and outputs I/O
-I/O
11
15
is loaded into a data-in register on the LOW-to-HIGH transition of
outputs are enabled. When OE is HIGH, the I/O outputs are in
1
DESCRIPTION
and EOB
Military and Commercial Temperature Ranges
2
are dependent on separate internal registers, and
0
-I/O
12
, are used to access the
8
-I/O
CC
15
supply.
in the same manner and
0
-I/O
1
and SSTRT
7
are tri-
3099 tbl 02
3099 tbl 01
2