IDT70824L25PF8 IDT, Integrated Device Technology Inc, IDT70824L25PF8 Datasheet - Page 8

• Manufacturer Part Number: IDT70824L25PF8
• Description: IC SARAM 64KBIT 25NS 80TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70824L25PF8

• Format - Memory: RAM
• Memory Type: SARAM
• Memory Size: 64K (4K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70824L25PF8

Truth Table: Sequential Address Pointer Operations
NOTES:
1. H = V
2. RST is continuously HIGH. The conditions of SCE CNTEN, and SR/W are unrelated to the sequential address pointer operations.
3. CE, OE, R/W, LB, UB, and I/O
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented
6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
Address Pointer Load Control (SLD)
pointer changes in the cycle following SLD. When SLD is LOW, data on
the inputs SI/O
HIGH transition of SCLK. On the cycle following SLD, the address pointer
SLD Mode
NOTE:
1. At SCLK edge (A), SI/O
Sequential Load of Address into Pointer/Counter
SSTRT
MSB
NOTE:
1. "H" = V
SCLK
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
port operation (due to the counter and register control). CMD should be HIGH (CMD = V
during the two cycles.
In SLD mode, there is an internal delay of one cycle before the address
address pointer changes). At SCLK edge (A), SSTRT
SLD and SSTRT
(B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
↑
↑
↑
SI/O
SCLK
(1 or 2)
IH
15
H
SLD
, L = V
IH
0-11
SLD
and "L" = V
H
H
L
(1)
0
-SI/O
IL
14
H
, X = Don't Care, and High-Z = High-impedance.
Inputs/Outputs
1,2
(1)
SSTRT
must be HIGH to ensure for proper sequential address pointer loading. For SSTRT
11
IL
H
H
L
for the SI/O intput state.
is loaded into a data-in register on the LOW-to-
13
0
H
-SI/O
1
0
11
-I/O
12
data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e.
L
SSTRT
15
are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential
H
L
H
1
11 --------------------------------------------------------------------------------------------------
SOE
H
X
X
(6)
Non-Counter Advanced Sequential Write, without EOB
Counter Advanced Sequential Write with EOB
No Write or Read due to Sequential port Deselect. No counter advance.
1
and SSTRT
2
must be HIGH to ensure for proper sequential address pointer loading. At SCLK edge (B),
A
ADDR
Address Loaded into Pointer
IN
8
changes to the address location contained in the data-in register. SSTRT
SSTRT
SLD. The SSTRT
addresses are pre-loaded in the registers already.
IH
) during sequential port access.
2
may not be low while SLD is LOW, or during the cycle following
1
1
and SSTRT
Military and Commercial Temperature Ranges
1
and EOB
MODE
or SSTRT
(1)
B
1
or EOB
2
(1,2,3,4,5)
2
reached.
, the data to be read will be ready for edge
2
require only one clock cycle, since these
2
reached.
DATA
0
LSB SI/O BITS
OUT
C
3099 drw 08
3099 drw 09
3099 tbl 14
1
,