IDT70824S20PF IDT, Integrated Device Technology Inc, IDT70824S20PF Datasheet - Page 13
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IDT70824S20PF
Manufacturer Part Number
IDT70824S20PF
Description
IC SARAM 64KBIT 20NS 80TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT70824S35PF8.pdf
(21 pages)
Specifications of IDT70824S20PF
Format - Memory
RAM
Memory Type
SARAM
Memory Size
64K (4K x 16)
Speed
20ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70824S20PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT70824S20PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT70824S20PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Waveform of Write Cycle No.1 (R/W Controlled Timing)
Random Access Port
Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing)
Random Access Port
NOTES:
1. R/W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/W = V
3. t
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. OE is continuously HIGH, OE = V
7. I/O
8. CMD access follows the standard CE access described above. If CMD = V
CE, LB, UB
CE, LB, UB
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
turn off and on the data to be placed on the bus for the required t
write pulse is the specified t
WR
I/O
ADDR
ADDR
OUT
is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
I/O
I/O
R/W
R/W
OUT
OE
is never enabled, therefore the output is in High-Z state during the entire write cycle.
IN
IN
(8)
(8)
t
AS
WP
. For the CE controlled write cycle, OE may be LOW with no degregation to t
IH
. If during the R/W controlled write cycle the OE is LOW, t
t
AS
(5)
(1,6)
(1,6,7)
Data Out
IL
, CE = V
(5)
IL
(4)
t
and LB = V
ACS
t
BE
DW
. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum
IL
and/or UB = V
IL
t
6.42
, then CE must = V
WHZ
13
t
AW
t
AW
t
WP
t
t
CW
BP
t
IL
WC
t
.
(2)
WC
(2)
(2)
WP
IH
must be greater or equal to t
Valid Data In
or, when CE = V
Military and Commercial Temperature Ranges
t
t
DW
DW
CW
Valid Data
timing.
IL
, CMD must = V
WHZ
t
DH
t
+ t
OW
DW
IH
t
.
DH
to allow the I/O drivers to
t
WR
t
t
OHZ
WR
Data Out
(3)
(3)
3099 drw 16
3099 drw 15
(4)