IDT70824S20G IDT, Integrated Device Technology Inc, IDT70824S20G Datasheet - Page 10

• Manufacturer Part Number: IDT70824S20G
• Description: IC SARAM 64KBIT 20NS 84PGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70824S20G

• Format - Memory: RAM
• Memory Type: SARAM
• Memory Size: 64K (4K x 16)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70824S20G

Flow Control Register Description
NOTES:
1. "H" = V
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously
Flow Control Bits
NOTES:
1. EOB
2. CMD flow control bits are unchanged, the count does not continue advancement.
3. If EOB
4. If the counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK; otherwise the flow
5. Flow Control Bit settings of '10' and '11' are reserved.
6. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode"
Cases 6 and 7: Flag Status Register Bit Description
Cases 6: Flag Status Register
Write Conditions
NOTES:
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
Cases 8 and 9: (Reserved)
NOTE:
1. "H" = V
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
MSB
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
MSB
(Bit 3 & Bit 2)
of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is
also released by RST, SLD, SSTRT
control will remain in the stop mode.
section. RST conditions are not set to valid addresses.
cleared while the second is left alone, or both may be cleared.
Bit 1 & Bit 0
Flag Status Bit 0, (Bit 1)
1
00
01
and EOB
1
15
OH
H
OH
15
and EOB
H
Flow Control
for I/O in the output state and "Don't Cares"' for I/O in the input state.
for I/O in the output state and "Don't Cares" for I/O in the input state.
0
1
H
2
H
2
may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
are equal, then the pointer will jump to the start of Buffer #1.
CHAINING
BUFFER
H
Mode
STOP
H
H
Clears Buffer Flag EOB
No chang e to the Buffer Flag.
H
(1)
(5)
1
on the next clock's rising edge. Otherwise, the address po inter will stop incrementing on EOB. Sequential write
operations are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow
control register.
EOB
The pointer value is changed to the start address of Buffer #2 (Buffer #1)
EOB
The address pointer will stop inc rementing when it reaches the next address (EOB address + 1), if CNTEN is LOW
and SSTRT
H
1
1
H
Functional Description
(EOB
(EOB
H
2
2
) is asserted (Active LOW output) when the pointer matches the end address of Buffer #1 (Buffer #2).
) is asserted when the pointer matches the end address of Butler #1 (Butler #2).
H
2
operations.
(1,2,4)
H
1
, (EOB
H
H
(2)
2
).
H
3099 tbl 18
H
(1,2)
H
10
H
Case 7: Flag Status Register Read
Conditions
H
Flag Status Bit 0, (Bit 1)
Functional Description
H
Counter Release
(STOP Mode Only)
H
H
0
1
4
Military and Commercial Temperature Ranges
H
Buffer #2 flow control
3
H
(1)
End of buffer flag for Buffer #2
(1,3)
Pointer has not reached the End of the
Buffer.
Pointer has reached the end of the
Buffer.
EOB
EOB
2
1
End of buffer flag for Buffer #1
1
1
Buffer #1 flow control
(EOB
(EOB
Functional Description
1
0
0
2
2
) flag has not been set, the
) flag has been set, the
LSB I/O BITS
0
0
LSB I/O BITS
3099 drw 12
3099 drw 11
3099 tbl 17
3099 tbl 19