MT48H8M16LFB4-8 TR Micron Technology Inc, MT48H8M16LFB4-8 TR Datasheet - Page 15

• Manufacturer Part Number: MT48H8M16LFB4-8 TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1052-2

Commands
Table 6:
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or DEEP POWER-DOWN
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER/LOAD EXTENDED MODE
REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
Truth Table 1 – Commands and DQM Operation
Note
1
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
Truth Table 1 provides a quick reference of available commands. This is followed by a
written description of each command. Three additional Truth Tables appear following
"Operation" on page 18; these tables provide current state/next state information.
10. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
2. A0-A11 define op-code written to mode register.
3. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0–A8 provide column address; A10 HIGH enables the auto precharge feature (non persis-
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks pre-
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
9. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when CKE
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which
bank is being read from or written to.
charged and BA0, BA1 are “Don’t Care.”
except for CKE.
delay). DQML controls DQ0–7, DQMH controls DQ8–15.
is LOW.
could coincide with data on the bus. However the DQs column reads a “Don’t Care” state
to illustrate that the BURST TERMINATE command can occur when there is no data
present.
CS# RAS# CAS# WE#
H
X
X
L
L
L
L
L
L
L
L
15
H
H
H
H
X
X
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
L
L
128Mb: x16 Mobile SDRAM
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
Bank, A10
Bank/Row
Bank/Col
Bank/Col
Op-Code
©2003 Micron Technology, Inc. All rights reserved.
ADDR
X
X
X
X
X
X
High-Z
Active
Valid
DQs
Commands
X
X
X
X
X
X
X
X
Notes
9, 10
6, 7
3
4
4
5
2
8
8