MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet
MT46H8M16LFCF-10
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MT46H8M16LFCF-10 Summary of contents
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Mobile DDR SDRAM MT46H8M16LF – 2 Meg Banks For the latest data sheet, refer to Micron’s Web site: Features • +1.8 ±0.1V +1.8 ±0. • Bidirectional data strobe per ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 60-Ball VFBGA Assignment (Top View ...
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List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Part Number MT46H8M16LFCF-75:B MT46H8M16LFCF-75IT:B MT46H8M16LFCF-10:B MT46H8M16LFCF-10IT:B FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s new FBGA Part Marking Decoder makes it easier to understand this part marking. Visit the Web site at www ...
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... REGISTER 2 9 PDF: 09005aef822b7e27/Source: 09005aef822b7dd6 MT46H8M16LFB_2.fm - Rev. A 5/06 EN 128Mb: 8 Meg x 16 Mobile DDR SDRAM BANK3 BANK2 BANK1 12 BANK0 13 ROW- BANK0 ADDRESS MEMORY 4,096 LATCH ARRAY & (4,096 x 256 x 32) DECODER SENSE AMPLIFIERS 8,192 I/O GATING DM MASK LOGIC BANK CONTROL LOGIC 256 ...
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... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ or WRITE commands, to select one location out of the memory array in the respective bank. During a PRECHARGE command, A10 determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...
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... Functional Description The 128Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728-bits internally configured as a quad-bank DRAM. Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. The 128Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high- speed operation ...
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... LOAD MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again. Reprogramming the standard mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the speci- fied time before initiating the subsequent operation ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by ...
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Table 5: Burst Definition Burst Length Notes: 1. For A1–Ai select the two-data-element block; A0 selects the first access within the block. 2. For A2–Ai select the four-data-element block; A0–A1 select ...
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Figure 4: CAS Latency CK# COMMAND DQS DQ CK# COMMAND DQS DQ Notes the cases shown. 2. Shown with nominal Operating Mode The normal operating mode is selected by issuing a LOAD MODE REGISTER SET ...
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... Because the Mobile DDR SDRAM is designed for use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available. Drive strength should be selected based on the expected loading of the memory bus. Bits A5 and A6 of the extended mode register can be used to select the driver strength of the DQ outputs ...
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Stopping the External Clock One method of controlling the power efficiency in applications is to throttle the clock which controls the SDRAM. There are two basic ways to control the clock: 1. Change the clock frequency, when the data transfers ...
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Commands Table 7 and Table 8 provide quick references of available commands. This is followed by a written description of each command. Three additional Truth Tables (Table 9 on page 42, Table 10 on page 43, and Table 11 on ...
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... WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coinci- dent with the data given DM signal is registered LOW, the corresponding data will be written to memory ...
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READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines ...
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AUTO REFRESH command except CKE is disabled (LOW). All command and address input signals except CKE are “Don’t Care” during SELF REFRESH. During SELF REFRESH, the device is refreshed as identified in the external mode ...
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Operations Bank/row Activation Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank ...
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Figure 8: Example: Meeting T0 T1 CK# CK COMMAND ACT NOP A0–A11 Row BA0, BA1 Bank x READs READ bursts are initiated with a READ command, as shown in Figure 9 on page 21. The starting column and bank addresses ...
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Figure 9: READ Command CK# CK CKE CS# RAS# CAS# WE# A0–A8 A11 A10 BA0,1 Notes: 1. DIS AP = Disable auto precharge Enable auto precharge BA = Bank address CA = Column address PDF: 09005aef822b7e27/Source: 09005aef822b7dd6 ...
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Figure 10: READ Burst CK# COMMAND ADDRESS DQS DQ CK# COMMAND ADDRESS DQS DQ Notes OUT Shown with nominal PDF: 09005aef822b7e27/Source: 09005aef822b7dd6 MT46H8M16LFB_2.fm - Rev. A 5/06 EN 128Mb: 8 Meg x 16 ...
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Figure 11: Consecutive READ Bursts CK# COMMAND ADDRESS DQS DQ CK# COMMAND COMMAND ADDRESS ADDRESS DQS DQ Notes OUT the cases shown (applies for bursts well). 3. Shown with nominal ...
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Figure 12: Nonconsecutive READ Bursts CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ Notes OUT the cases shown (applies for bursts well). 3. Shown with nominal ...
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Figure 13: Random READ Accesses CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND COMMAND ADDRESS ADDRESS DQS DQ Notes OUT the cases shown (applies for bursts well). 3. READs ...
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Figure 14: Terminating a READ Burst CK# COMMAND ADDRESS DQS CK# COMMAND ADDRESS DQS Notes OUT 2. Only valid for and Shown with nominal 4. BST = BURST TERMINATE command; page ...
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Figure 15: READ-to-WRITE CK# COMMAND ADDRESS DQS DQ DM CK# COMMAND ADDRESS DQS DQ DM Notes OUT the cases shown (applies for bursts well ...
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Figure 16: READ-to-PRECHARGE CK# COMMAND ADDRESS DQS CK# COMMAND ADDRESS DQS Notes OUT interrupted burst Shown with nominal 4. READ-to-PRECHARGE equals 2 clocks, which allows 2 data pairs of ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 17 on page 30. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. ...
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Figure 17: WRITE Command CK# CK CKE CS# RAS# CAS# WE# A0–A8 A11 A10 BA0,1 Notes: 1. DIS AP = Disable auto precharge Enable auto precharge BA = Bank address CA = Column address PDF: 09005aef822b7e27/Source: 09005aef822b7dd6 ...
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Figure 18: WRITE Burst CK# COMMAND ADDRESS t DQSS (NOM) DQS DQSS (MIN) DQS DQSS (MAX) DQS DQ DM Notes uninterrupted burst shown. 3. A10 is ...
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Figure 19: Consecutive WRITE-to-WRITE COMMAND ADDRESS t DQSS (NOM) Notes uninterrupted burst shown. 3. Each WRITE command may be to any bank. Figure 20: Nonconsecutive WRITE-to-WRITE COMMAND ADDRESS t DQSS (NOM) Notes: ...
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Figure 21: Random WRITE Cycles CK# COMMAND ADDRESS DQS DQ DM Notes ( the next data-in following D burst order. 3. Programmed cases ...
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Figure 22: WRITE-to-READ – Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS DQSS (MAX) DQS DQ DM Notes: ...
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Figure 23: WRITE-to-READ – Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM ...
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Figure 24: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) ...
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Figure 25: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 26: WRITE-to-PRECHARGE – Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 27: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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PRECHARGE The PRECHARGE command (see Figure 28) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subse- quent row access some specified time ( ...
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Power-Down (Active or Precharge) Power-down (see Figure 30) is entered when CKE is registered LOW. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active ...
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Figure 30: Power-Down (Active or Precharge Referencing CKE and XP CKE COMMAND VALID t Referencing PDEX CKE COMMAND VALID No READ/WRITE access in progress Notes: 1. Clock must toggle a minimum of once during this ...
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Table 10: Truth Table – Current State Bank n - Command to Bank n Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle Row ...
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The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. 6. All states and sequences not shown are illegal or reserved. 7. Not ...
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Table 11: Truth Table – Current State Bank n - Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle X X Row L L activating, L ...
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WR ends, with period starts with registration of the command and ends where the precharge period (or This device supports concurrent auto precharge such that when a read with auto precharge enabled or a write with auto precharge is ...
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Electrical Specifications Stresses greater than those listed in Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 14: Capacitance Notes: 13; notes appear on pages 52–54 Parameter Delta input/output capacitance: DQs, DQS, DM Delta input capacitance: Command and address Delta input capacitance: CK, CK# Input/output capacitance: DQs, DQS, DM Input capacitance: Address Input capacitance: Command Input ...
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Table 15: I Specifications and Conditions (continued) DD Notes: 1–5, 7, 10, 12, 14 notes appear on pages 52–54; V Parameter/Condition Operating burst write: One bank active Continuous WRITE bursts; Address inputs are switching; 50 percent data ...
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Table 16: Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–6, 27; notes appear on pages 52–54 Characteristics Parameter Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time Auto precharge write recovery ...
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Table 16: Electrical Characteristics and Recommended AC Operating Conditions (continued) Notes: 1–6, 27; notes appear on pages 52–54 Characteristics Parameter DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ ...
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Notes 1. All voltages referenced to Vss. 2. All parameters assume proper device initialization. 3. Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ...
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HZ and tions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 16. The maximum limit for this parameter is not a ...
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V IH can not be greater than 1/3 of the cycle rate. V pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. t 34. HZ (MAX) will prevail over 35. ...
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Timing Diagrams Figure 32: x16 Data Output Timing – CK# CK LDQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) DQ0 - ...
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Figure 33: Data Output Timing – T0 CK# CK COMMAND READ 1 DQS, or LDQS/UDQS 2 All DQ values, collectively Notes transitioning after DQS transition define 2. All DQ must transition the DQ ...
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Figure 35: Initialize and Load Mode Registers ( ( ) ) CK LVCMOS HIGH LEVEL ( ( ) ) CKE ( ( ...
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Figure 36: Power-Down Mode (Active or Precharge CKE VALID 1 COMMAND ADDR VALID DQS DQ DM Power-Down Notes this command is ...
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Figure 37: Auto Refresh Mode CKE NOP 2 COMMAND PRE A0–A9, 1 A11, A11 ALL BANKS 1 A10 ONE BANK Bank(s) ...
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Figure 38: Self Refresh Mode CK# CKE COMMAND ADDR DQS DM Notes: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within specifications by Ta0. 2. Device must be in the all ...
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Figure 39: Bank Read – Without Auto Precharge CKE NOP 6 COMMAND ACT A0– A11, A12 A10 RA t ...
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Figure 40: Bank Read – With Auto Precharge CKE NOP 6 COMMAND ACT A0– A11, A12 A10 RA t ...
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Figure 41: Bank Write – Without Auto Precharge CKE NOP 6 COMMAND ACT A0- A11 A10 ...
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Figure 42: Bank Write – With Auto Precharge CKE NOP 5 COMMAND ACT A0- A11 A10 ...
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Figure 43: Write – DM Operation CKE NOP 6 COMMAND ACT A0–A9 A11 RA A10 ...
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Package Dimensions Figure 44: 60-Ball VFBGA Package SEATING PLANE C 0.10 C 60X Ø 0.45 6.40 SOLDER BALL DIAMETER REFERS 0.80 TYP TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.42 BALL A9 7.20 3.60 3.20 8.00 ±0.10 ...