MT48LC16M16A2TG-7E L:D TR Micron Technology Inc, MT48LC16M16A2TG-7E L:D TR Datasheet - Page 38

• Manufacturer Part Number: MT48LC16M16A2TG-7E L:D TR
• Description: IC SDRAM 256MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16A2TG-7E L:D TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Truth Tables
Table 17: Truth Table – Current State Bank n, Command to Bank n
Notes 1–6 apply to all parameters and conditions
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Current State
Any
Idle
Row active
Read
(auto precharge disabled)
Write
(auto precharge disabled)
Notes:
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table is bank-specific, except where noted (for example, the current state is for a
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank.
and after
specific bank and the commands shown can be issued to that bank when in that state).
Exceptions are covered below.
Idle: The bank has been precharged, and
Row active: A row in the bank has been activated, and
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank
should be issued on any clock edge occurring during these states. Supported commands
to any other bank are determined by the bank’s current state and the conditions descri-
bed in this and the following table.
Precharging: Starts with registration of a PRECHARGE command and ends when
met. After
Row activating: Starts with registration of an ACTIVE command and ends when
met. After
RAS# CAS#
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
t
XSR has been met (if the previous state was self refresh).
t
t
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
RP is met, the bank will be in the idle state.
RCD is met, the bank will be in the row active state.
WE# Command/Action
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
38
n-1
was HIGH and CKE
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP has been met.
256Mb: x4, x8, x16 SDRAM
n
is HIGH (see Table 19 (page 42))
t
RCD has been met. No data bursts/
© 1999 Micron Technology, Inc. All rights reserved.
Truth Tables
Notes
t
t
RCD is
RP is
10
10
11
10
11
7
7
8
9
9
9
9
9
9