MT45W1MW16BDGB-701 WT TR Micron Technology Inc, MT45W1MW16BDGB-701 WT TR Datasheet - Page 21
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MT45W1MW16BDGB-701 WT TR
Manufacturer Part Number
MT45W1MW16BDGB-701 WT TR
Description
IC PSRAM 16MBIT 70NS 54VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT45W1MW16BDGB-708_AT_TR.pdf
(59 pages)
Specifications of MT45W1MW16BDGB-701 WT TR
Format - Memory
RAM
Memory Type
PSRAM (Page)
Memory Size
16M (1M x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-30°C ~ 85°C
Package / Case
54-VFBGA
Operating Temperature (max)
85C
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1209-2
MT45W1MW16BDGB-701 WT TR
MT45W1MW16BDGB-701 WT TR
Software Access
Figure 15:
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
Load Configuration Register
Note:
Software access of the configuration registers uses a sequence of asynchronous READ
and asynchronous WRITE operations. The contents of the configuration registers can be
read or modified using the software sequence.
The configuration registers are loaded using a four-step sequence consisting of two
asynchronous READ operations followed by two asynchronous WRITE operations (see
Figure 15). The read sequence is virtually identical except that an asynchronous READ is
performed during the fourth operation (see Figure 16). Note that a third READ cycle of
the highest address will cancel the access sequence until a different address is read.
The address used during all READ and WRITE operations is the highest address of the
CellularRAM device being accessed (FFFFFh for 16Mb); the content at this address is not
changed by using this sequence.
The data value presented during the third operation (WRITE) in the sequence defines
whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will
access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth
operation, DQ[15:0] transfer data into or out of bits 15–0 of the configuration registers.
The use of the software sequence does not affect the ability to perform the standard
(CRE-controlled) method of loading the configuration registers. However, the software
nature of this access mechanism eliminates the need for the control register enable
(CRE) pin. If the software mechanism is used, the CRE pin can simply be tied to V
port line often used for CRE control purposes is no longer required.
Software access of the RCR should not be used to enter or exit DPD.
ADDRESS
LB#/UB#
DATA
WE#
OE#
If the data present when WE# falls is not 0000h or 0001h, it is possible that the maximum
address will be overwritten.
CE#
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
ADDRESS
(MAX)
XXXXh
READ
ADDRESS
(MAX)
XXXXh
READ
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RCR: 0000h
BCR: 0001h
ADDRESS
WRITE
(MAX)
Note 0ns (Min)
CR VALUE
ADDRESS
WRITE
Configuration Registers
(MAX)
DON'T CARE
IN
©2005 Micron Technology, Inc. All rights reserved.
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