MT45W1MW16BDGB-701 WT TR Micron Technology Inc, MT45W1MW16BDGB-701 WT TR Datasheet - Page 34
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MT45W1MW16BDGB-701 WT TR
Manufacturer Part Number
MT45W1MW16BDGB-701 WT TR
Description
IC PSRAM 16MBIT 70NS 54VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT45W1MW16BDGB-708_AT_TR.pdf
(59 pages)
Specifications of MT45W1MW16BDGB-701 WT TR
Format - Memory
RAM
Memory Type
PSRAM (Page)
Memory Size
16M (1M x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-30°C ~ 85°C
Package / Case
54-VFBGA
Operating Temperature (max)
85C
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1209-2
MT45W1MW16BDGB-701 WT TR
MT45W1MW16BDGB-701 WT TR
Table 13:
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
Parameter
Burst to READ access time
CLK to output delay
Burst OE# LOW to output delay
CE# HIGH between subsequent burst and
mixed-mode operations
Maximum CE# pulse width
CE# LOW to WAIT valid
CLK period
CE# setup time to active CLK edge
Hold time from active CLK edge
Chip disable to DQ and WAIT High-Z output
CLK rise or fall time
CLK to WAIT valid
Output HOLD from CLK
CLK HIGH or LOW time
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
1
Burst READ Cycle Timing Requirements
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).
2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The
4. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low-
vided every
tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns.
High-Z timings measure a 100mV transition from either V
Z timings measure a 100mV transition away from the High-Z (V
V
OH
or V
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
OL
.
t
CEM. A refresh opportunity is satisfied by either of the following two condi-
Symbol
t
t
t
t
t
t
t
t
t
ACLK
t
CBPH
KHKL
KHTL
t
t
t
ABA
CEM
CEW
t
KOH
OHZ
BOE
t
t
OLZ
CLK
CSP
t
HD
HZ
KP
SP
34
Min
9.62
5
1
3
2
2
3
3
3
104 MHz
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Max
7.5
1.6
35
20
20
20
7
8
8
7
8
Min
12.5
4.5
5
1
2
2
4
3
3
80 MHz
OH
or V
Timing Requirements
Max
46.5
CC
7.5
1.8
©2005 Micron Technology, Inc. All rights reserved.
20
20
20
9
8
8
9
8
OL
Q/2) level toward either
toward V
Units
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC
Q/2.
Notes
2
3
3
4