MT41J512M8THU-187E:A Micron Technology Inc, MT41J512M8THU-187E:A Datasheet - Page 99

• Manufacturer Part Number: MT41J512M8THU-187E:A
• Description: IC DDR3 SDRAM 4GBIT 82FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT41J512M8THU-187E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 4G (512M x 8)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 41: DLL Enable Mode to DLL Disable Mode
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Command
ODT 9
CKE
CK#
CK
6
MRS 2
T0
Notes:
t MOD
NOP
T1
3. After
4. Self refresh may be exited when the clock is stable with the new frequency for
5. The DRAM will be ready for its next command in the DLL disable mode after the
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is
2. After
3. Self refresh may be exited when the clock is stable with the new frequency for
4. After another
5. The DRAM will be ready for its next command in the DLL enable mode after the
1. Any valid command.
2. Disable DLL by setting MR1[0] to “1.”
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, R
7. Change frequency.
8. Clock must be stable
9. Static LOW in case R
A similar procedure is required for switching from the DLL disable mode back to the DLL
enable mode. This also requires changing the frequency during self refresh mode (see
Figure 42 on page 100).
After
greater of
appropriate timings met as well.
turned off, and R
After
imum, set MR1[0] to “0” to enable the DLL. Wait
enable DLL RESET.
the appropriate values.
greater of
or function requiring a locked DLL, a delay of
fied. A ZQCL command should be issued with the appropriate timings met as well.
SRE 3
Ta0
t
t
t
t
CKSRE is satisfied, change the frequency to the desired clock rate.
XS is satisfied, update the mode registers with appropriate values.
CKSRE is satisfied, change the frequency to the new clock rate.
XS is satisfied, update the mode registers with the appropriate values. At a min-
t
t
t CKSRE
MRD or
MRD or
NOP
Ta1
t
MRD delay is satisfied, then update the remaining mode registers with
TT
t
t
TT
_
t CKESR
MOD has been satisfied. A ZQCL command should be issued with
MOD has been satisfied. However, before applying any command
t
NOM
Tb0
CKSRX.
_
NOM
and R
7
or R
99
TT
is in the High-Z state.
TT
Tc0
TT
_
t CKSRX 8
WR
_
WR
is enabled; otherwise, static LOW or HIGH.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
are High-Z), enter self refresh mode.
SRX 4
Td0
t
2Gb: x4, x8, x16 DDR3 SDRAM
DLLK after DLL RESET must be satis-
NOP
Td1
t XS
t
MRD, then set MR0[8] to “1” to
Indicates a Break in
Time Scale
MRS 5
Te0
©2006 Micron Technology, Inc. All rights reserved.
t MOD
NOP
Te1
Commands
Don’t Care
Valid 1
Valid 1
Valid 1
Tf0
t
t
CKSRX.
CKSRX.