PSD813F1A-90M STMicroelectronics, PSD813F1A-90M Datasheet - Page 18
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PSD813F1A-90M
Manufacturer Part Number
PSD813F1A-90M
Description
IC FLASH 1MBIT 90NS 52QFP
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F1A-90U.pdf
(111 pages)
Specifications of PSD813F1A-90M
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1977
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD813F1A-90M
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
PSD813F1A-90MI
Manufacturer:
STMicroelectronics
Quantity:
10 000
PSD813F1A
DETAILED OPERATION
As shown in
of six major types of functional blocks:
■
■
■
■
■
■
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKS
The PSD has the following memory blocks (see
Table 7):
–
–
–
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary
EEPROM Description
The 1Mb primary Flash memory is divided evenly
into eight 16-KByte sectors. The EEPROM memo-
ry is divided into four sectors of eight KBytes each.
Each sector of either memory can be separately
protected from Program and Erase operations.
Flash memory may be erased on a sector-by-sec-
tor basis and programmed byte-by-byte. Flash
sector erasure may be suspended while data is
read from other sectors of memory and then re-
sumed after reading.
EEPROM may be programmed byte-by-byte or
sector-by-sector, and erasing is automatic and
18/111
Memory Blocks
PLD Blocks
MCU Bus Interface
I/O Ports
Power Management Unit (PMU)
JTAG Interface
The Main Flash memory
Secondary EEPROM memory
SRAM
Figure 5., page
13, the PSD consists
transparent. The integrity of the data can be se-
cured with the help of Software Data Protection
(SDP). Any write operation to the EEPROM is in-
hibited during the first five milliseconds following
power-up.
During a program or erase of Flash, or during a
write of the EEPROM, the status can be output on
the Ready/Busy (PC3) pin of Port C3. This pin is
set up using PSDsoft Express Configuration.
Memory Block Select Signals. The
PLD in the PSD generates the chip selects for all
the internal memory blocks (refer to the section
entitled
memory sectors have a Flash Select signal (FS0-
FS7) which can contain up to three product terms.
Each of the four EEPROM memory sectors have a
Select signal (EES0-3 or CSBOOT0-3) which can
contain up to three product terms. Having three
product terms for each sector select signal allows
a given sector to be mapped in different areas of
system memory. When using a microcontroller
with separate Program and Data space, these
flexible select signals allow dynamic re-mapping of
sectors from one space to the other.
Ready/Busy Pin (PC3). Pin PC3 can be used to
output the Ready/Busy status of the PSD. The out-
put on the pin will be a ‘0’ (Busy) when Flash or
EEPROM memory blocks are being written to, or
when the Flash memory block is being erased.
The output will be a ‘1’ (Ready) when no write or
erase operation is in progress.
Table 7. Memory Blocks
PSD813F1A
Device
PLD’S, page
Main Flash
128KB
34). Each of the eight Flash
EEPROM
32KB
decode
SRAM
2KB