PSD813F1A-90M STMicroelectronics, PSD813F1A-90M Datasheet - Page 23
![IC FLASH 1MBIT 90NS 52QFP](/photos/7/25/72513/497-52-pqfp_series_sml.jpg)
PSD813F1A-90M
Manufacturer Part Number
PSD813F1A-90M
Description
IC FLASH 1MBIT 90NS 52QFP
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F1A-90U.pdf
(111 pages)
Specifications of PSD813F1A-90M
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1977
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD813F1A-90M
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
PSD813F1A-90MI
Manufacturer:
STMicroelectronics
Quantity:
10 000
Data Polling Flag (DQ7)
When Erasing or Programming the Flash memory
(or when Writing into the EEPROM memory), bit
DQ7 outputs the complement of the bit being en-
tered for Programming/Writing on DQ7. Once the
Program instruction or the WRITE operation is
completed, the true logic value is read on DQ7 (in
a Read operation). Flash memory specific fea-
tures:
–
–
–
–
Toggle Flag (DQ6)
The PSD offers another way for determining when
the EEPROM write or the Flash memory Program
instruction is completed. During the internal
WRITE operation and when either the FSi or EESi
is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to
‘0’ on subsequent attempts to read any byte of the
memory.
When the internal cycle is complete, the toggling
will stop and the data read on the Data Bus D0-7
is the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
Data Polling is effective after the fourth WRITE
pulse (for programming) or after the sixth
WRITE pulse (for Erase). It must be performed
at the address being programmed or at an
address within the Flash sector being erased.
During an Erase instruction, DQ7 outputs a ‘0.’
After completion of the instruction, DQ7 will
output the last bit programmed (it is a ‘1’ after
erasing).
If the byte to be programmed is in a protected
Flash sector, the instruction is ignored.
If all the Flash sectors to be erased are
protected, DQ7 will be set to ‘0’ for about
100µs, and then return to the previous
addressed byte. No erasure will be performed.
■
■
■
Error Flag (DQ5)
During a correct Program or Erase, the Error bit
will set to ‘0.’ This bit is set to ‘1’ when there is a
failure during Flash byte programming, Sector
erase, or Bulk Erase.
In the case of Flash programming, the Error Bit in-
dicates the attempt to program a Flash bit(s) from
the programmed state ('0') to the erased state ('1'),
which is not a valid operation. The Error bit may
also indicate a timeout condition while attempting
to program a byte.
In case of an error in Flash sector erase or byte
program, the Flash sector in which the error oc-
curred or to which the programmed byte belongs
must no longer be used. Other Flash sectors may
still be used. The Error bit resets after the Reset in-
struction.
Erase Time-out Flag DQ3 (Flash Memory only)
The Erase Timer bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase timer bit is set to ‘0’ after a
Sector Erase instruction for a time period of 100µs
+ 20% unless an additional Sector Erase instruc-
tion is decoded. After this time period or when the
additional Sector Erase instruction is decoded,
DQ3 is set to ‘1.’
The operation is finished when two successive
reads yield the same output data. Flash memory
specific features:
The Toggle bit is effective after the fourth
WRITE pulse (for programming) or after the
sixth WRITE pulse (for Erase).
If the byte to be programmed belongs to a
protected Flash sector, the instruction is
ignored.
If all the Flash sectors selected for erasure are
protected, DQ6 will toggle to ‘0’ for about 100
µs and then return to the previous addressed
byte.
PSD813F1A
23/111