NAND256W3A2BN6E NUMONYX, NAND256W3A2BN6E Datasheet
NAND256W3A2BN6E
Specifications of NAND256W3A2BN6E
497-5038
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NAND256W3A2BN6E Summary of contents
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... Lead-free components are compliant with Development tools – Error correction code software and – Bad blocks management and wear leveling – File system OS native reference software – Hardware simulation models Rev 16 TSOP48 FBGA VFBGA55 1.05 mm transitions the RoHS directive hardware models algorithms 1/59 www.numonyx.com 1 ...
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... Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Inputs/outputs (I/O0-I/O7 3.2 Inputs/outputs (I/O8-I/O15 3.3 Address Latch Enable (AL 3.4 Command Latch Enable (CL 3.5 Chip Enable ( 3.6 Read Enable ( 3.7 Write Enable ( 3.8 Write Protect (WP 3.9 Ready/Busy (RB ...
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NAND128-A, NAND256-A 6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. NAND128-A and NAND256-A device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... TSOP48 connections, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. TSOP48 connections, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. VFBGA55 connections, x8 devices (top view through package Figure 6. VFBGA55 connections, x16 devices (top view through package Figure 7. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Pointer operations Figure 9. Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Read ( operations Figure 11. ...
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Description 1 Description The NAND flash 528-byte/264-word page is a family of non-volatile flash memories that uses the single level cell (SLC) NAND technology, referred to as the SLC small page family. The devices are either 128 Mbits or 256 ...
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... Serial number (unique identifier), which enables each device to be uniquely identified subject to an NDA and is, therefore, not described in the datasheet. For more details about these security features, contact your nearest Numonyx sales office. For information on how to order these devices refer to scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits in valid blocks erased to ’ ...
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Description Figure 1. Logic diagram Table 3. Signal names Symbol I/O8-15 Data input/outputs for x16 devices Data input/outputs, address inputs, or command inputs for x8 and x16 I/O0-7 devices AL Address Latch Enable CL Command Latch Enable E Chip Enable ...
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... NAND128-A, NAND256-A Figure 2. Logic block diagram Address register/counter Command interface E logic WP R Command register NAND flash memory array P/E/R controller, high voltage generator Page buffer Y decoder I/O buffers & latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 Description AI07561c 9/59 ...
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Description Figure 3. TSOP48 connections, x8 devices 10/ NAND flash (x8 ...
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NAND128-A, NAND256-A Figure 4. TSOP48 connections, x16 devices NAND flash (x16 ...
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Description Figure 5. VFBGA55 connections, x8 devices (top view through package 12/ ...
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NAND128-A, NAND256-A Figure 6. VFBGA55 connections, x16 devices (top view through package ...
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... Memory array organization The memory array comprises NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the main area and the spare area. The main area of the array stores data, whereas the spare area is typically used to store error correction codes, software flags or bad block identification ...
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... Page = 528 bytes (512+16) 2nd half page (256 bytes) Block Page 8 bits 16 bytes 16 512 bytes 8 bits bytes Memory array organization x16 DEVICES Block = 32 pages Page = 264 words (256+8) Main area 16 bits 256 words 8 words Page buffer, 264 words 8 256 words words ...
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... When CL is high, the inputs are latched on the rising edge of Write Enable. 3.5 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, V While the device is busy programming or erasing, Chip Enable transitions to High (V ignored and the device does not go into standby mode ...
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... V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V (see paragraph Figure 35: Data program/erase operations during power-transitions ...
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Signal descriptions 3.11 V ground SS Ground the reference for the power supply. It must be connected to the system SS, ground. 18/59 NAND128-A, NAND256-A ...
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... NAND128-A, NAND256-A 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see 4.1 Command input Command input bus operations give commands to the memory. Commands are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low, and Read Enable is High ...
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... Bus operations 4.4 Data output Data output bus operations read the data in the memory array, the status register, the electronic signature, and the serial number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. ...
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NAND128-A, NAND256-A Table 7. Address insertion, x16 devices I/O8- Bus Cycle I/O15 ’don’t care’ in x16 devices. 2. Any additional address input cycles are ignored. 3. The 01h ...
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Command set 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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... The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device. In x16 devices the Read A command (00h) sets the pointer to Area A (the whole of the main area), that is words 0 to 255 ...
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... I/O 50h 6.2 Read memory array Each operation to read the memory area starts with a pointer operation as shown in the Section 6.1: Pointer Read A, Read B or Read C commands three bus cycles are required to input the address of the data to be read. The device defaults to Read A mode after power- reset operation. ...
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NAND128-A, NAND256-A and Chip Enable remains Low, then the next page is automatically loaded into the page buffer and the read operation continues. A sequential row read operation can only be used to read within a block. If the block ...
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Device operations Figure 12. Sequential row read operations (Read busy time) RB 00h/ I/O Address inputs 01h/ 50h Command code Figure 13. Sequential row read block diagrams Read A command, x8 devices Area B Area A (2nd half Page) (1st ...
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... NAND128-A, NAND256-A 6.3 Page program The page program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. ...
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... The copy back program operation copies the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block ...
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... The Reset command resets the command interface and status register. If the Reset command is issued during any operation, the operation is aborted was a program or erase operation that was aborted, the contents of the memory locations being modified are no longer valid as the data is partially programmed or erased. ...
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... The error bit identifies if any errors have been detected by the P/E/R controller. The error bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to ‘0’ the operation has completed successfully. SR5, SR4, SR3, SR2 and SR1 are reserved. ...
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NAND128-A, NAND256-A Refer to Table 12 Table 12. Electronic signature Part number NAND128W3A NAND256W3A NAND256W4A for information on the addresses. Manufacturer code Device operations Device code 20h 73h 20h 75h 0020h 0055h 31/59 ...
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... For the integration of NAND memories into an application, Numonyx provides a full range of software solutions such as file systems, sector managers, drivers, and code management. Contact the nearest Numonyx sales office or visit www.numonyx.com for more details. ...
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NAND128-A, NAND256-A Refer to Table 13 operation. Table 13. Block failure Operation Erase Program Read Figure 17. Bad block management flowchart for the recommended procedure to follow if an error occurs during an START Block Address = Block 0 Data ...
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... After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a garbage collection algorithm garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 18: Garbage Figure 18 ...
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NAND128-A, NAND256-A 7.5 Error correction code An error correction code (ECC) can be implemented in the NAND flash memories to identify and correct errors in the data. The recommendation is to implement 23 bits of ECC for every 4096 bits ...
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Program and erase times and endurance cycles 8 Program and erase times and endurance cycles The program and erase times and the number of program/ erase cycles per block are shown in Table 14. Table 14. Program, erase times and ...
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NAND128-A, NAND256-A 9 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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DC and AC parameters 10 DC and AC parameters This section summarizes the operating and measurement conditions and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables in this section are derived ...
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NAND128-A, NAND256-A Figure 20. Equivalent testing circuit for AC characteristics measurement V DD NAND Flash C L GND DC and AC parameters 2R ref 2R ref GND Ai11085 39/59 ...
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DC and AC parameters Table 18. DC characteristics Symbol I DD1 Operating current I DD2 I DD3 I Standby current (TTL) DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input High ...
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NAND128-A, NAND256-A t Table 19. AC characteristics for command, address, data input Alt. Symbol symbol t Address Latch Low to Write Enable Low ALLWL t ALS t Address Latch High to Write Enable Low ALHWL t Command Latch High to ...
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DC and AC parameters Table 20. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 Ready/Busy Low ...
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NAND128-A, NAND256-A Figure 21. Command Latch AC waveforms I/O Figure 22. Address Latch AC waveforms CL tELWL (E Setup time tALHWL (AL Setup time) AL I/O tCLHWL (CL Setup time) tELWL (E Setup time) ...
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DC and AC parameters Figure 23. Data Input Latch AC waveforms CL E tALLWL (ALSetup time I/O Figure 24. Sequential data output after read AC waveforms Low Low High. 44/59 tWLWL ...
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NAND128-A, NAND256-A Figure 25. Read status register AC waveform Figure 26. Read electronic signature AC waveform I/O Read Electronic 1. Refer to Table 12: Electronic signature tALLRL1 tRLQV (Read ES Access time) Man. 90h 00h ...
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... Command Code Figure 28. Read C operation, one page AC waveform I/O RB Command Code 1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’. 46/59 tWLWL tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N Add.N N ...
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NAND128-A, NAND256-A Figure 29. Page program AC waveform I/O 80h RB Page Program Setup Code Figure 30. Block erase AC waveform I/O RB Block Erase Setup Command tWLWL tWLWL (Write ...
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DC and AC parameters Figure 31. Reset AC waveform I/O RB 10.1 Ready/busy signal electrical characteristics Figures Figure 32, Ready/Busy signal. The value required for the resistor R following equation: Therefore, where I is the sum ...
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NAND128-A, NAND256-A Figure 33. Ready/busy load circuit Figure 34. Resistor value versus waveform timings for Ready/Busy signal ° DEVICE RB Open Drain Output and AC parameters ibusy AI07563B 49/59 ...
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... DC and AC parameters 10.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD Low ( guarantee hardware protection during power transitions as shown in the below IL figure. Figure 35. Data protection V DD ...
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... NAND128-A, NAND256-A 11 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Package mechanical Figure 37. VFBGA55 active ball array, 0.8 mm pitch, package outline 1. Drawing is not to scale. 52/ FE1 FD1 ...
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NAND128-A, NAND256-A Table 22. VFBGA55 1. ball array, 0.8 mm pitch, package mechanical data Symbol ddd FD1 ...
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... F = RoHS compliant package, tape and reel packing 1. 1. x16 organization only available for MCP. Note: Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. 54/59 NAND128-A, NAND256-A NAND128 ...
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... NAND I/O in different address spaces inside the same chip select unit, which improves the setup and hold times and simplifies the firmware. The structure uses the microcontroller DMA (direct memory access) engines to optimize the transfer between the NAND flash and the system RAM. ...
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Hardware interface examples Figure 39. Connection to microcontroller, with glue logic Microcontroller Figure 40. Building storage modules NAND Flash W Device 56/ CSn A3 CLK ...
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NAND128-A, NAND256-A 13 Revision history Table 24. Document revision history Date Version 06-Jun-2003 07-Aug-2003 27-Oct-2003 03-Dec-2003 13-Apr-2004 28-May-2004 02-Jul-2004 01-Oct-2004 03-Dec-2004 1 Initial release 2 Design phase 3 Engineering phase Document promoted from Target Specification to Preliminary Data status. V ...
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... TSOP48 connections, x16 devices Removed all information pertaining to the 512-Mbit and 1-Gbit devices. 14 Applied Numonyx branding. Removed all the information pertaining the 1.8 V devices (V 15 1.95 V) and the USOP48 and VFBGA63 packages. Added the sequential row read option throughout the document. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...