NAND128W3A0AN6F STMicroelectronics, NAND128W3A0AN6F Datasheet - Page 30
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NAND128W3A0AN6F
Manufacturer Part Number
NAND128W3A0AN6F
Description
IC FLASH 128MBIT 48TSOP
Manufacturer
STMicroelectronics
Datasheet
1.NAND128W3A2BN6E.pdf
(56 pages)
Specifications of NAND128W3A0AN6F
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
128M (16M x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 22. Bad Block Management Flowchart
Figure 23. Garbage Collection
Garbage Collection
When a data page needs to be modified, it is faster
to write to the first available page, and the previous
page is marked as invalid. After several updates it
is necessary to remove invalid pages to free some
memory space.
To free this memory space and allow further pro-
gram operations it is recommended to implement
a Garbage Collection algorithm. In a Garbage Col-
lection software the valid pages are copied into a
free area and the block containing the invalid pag-
es is erased (see
30/56
Block Address =
START
Block 0
= FFh?
block?
Data
Last
END
YES
YES
Figure
Invalid
Valid
Page
Page
NO
NO
23.).
Bad Block table
Update
Block Address
Increment
Old Area
AI07588C
(Erased)
Free
Page
Wear-leveling Algorithm
For write-intensive applications, it is recommend-
ed to implement a Wear-leveling Algorithm to
monitor and spread the number of write cycles per
block.
In memories that do not use a Wear-Leveling Al-
gorithm not all blocks get used at the same rate.
Blocks with long-lived data do not endure as many
write cycles as the blocks with frequently-changed
data.
The Wear-leveling Algorithm ensures that equal
use is made of all the available write cycles for
each block. There are two wear-leveling levels:
New Area (After GC)
AI07599B