NAND512W3A0AN6 STMicroelectronics, NAND512W3A0AN6 Datasheet - Page 15
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NAND512W3A0AN6
Manufacturer Part Number
NAND512W3A0AN6
Description
IC FLASH 512MBIT 48TSOP
Manufacturer
STMicroelectronics
Datasheet
1.NAND128W3A2BN6E.pdf
(56 pages)
Specifications of NAND512W3A0AN6
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
512M (64M x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NAND512W3A0AN6
Manufacturer:
ST
Quantity:
106
Part Number:
NAND512W3A0AN6
Manufacturer:
ST
Quantity:
20 000
MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structures
where 16 cells are connected in series.
The memory array is organized in blocks where
each block contains 32 pages. The array is split
into two areas, the main area and the spare area.
The main area of the array is used to store data
whereas the spare area is typically used to store
Error correction Codes, software flags or Bad
Block identification.
In x8 devices the pages are split into a main area
with two half pages of 256 Bytes each and a spare
area of 16 Bytes. In the x16 devices the pages are
split into a 256 Word main area and an 8 Word
spare area. Refer to
ganization.
Bad Blocks
The NAND Flash 528 Byte/ 264 Word Page devic-
es may contain Bad Blocks, that is blocks that con-
tain one or more invalid bits whose reliability is not
guaranteed. Additional Bad Blocks may develop
during the lifetime of the device.
Figure 10. Memory Array Organization
Block
Page
1st half Page
(256 bytes)
512 Bytes
Page Buffer, 512 Bytes
Figure 10., Memory Array Or-
2nd half Page
512 Bytes
Block = 32 Pages
Page = 528 Bytes (512+16)
(256 bytes)
x8 DEVICES
Bytes
Bytes
16
16
8 bits
8 bits
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Block
Page
The Bad Block Information is written prior to ship-
ping (refer to
more details).
Table 4.
blocks in each device. The values shown include
both the Bad Blocks that are present when the de-
vice is shipped and the Bad Blocks that could de-
velop later on.
These blocks need to be managed using Bad
Blocks Management, Block Replacement or Error
Correction Codes (refer to
RITHMS
Table 4. Valid Blocks
Density of Device
512Mbits
256Mbits
128Mbits
1Gbit
section).
shows the minimum number of valid
256 Words
Main Area
Page Buffer, 264 Words
Bad Block Management
256 Words
Block = 32 Pages
Page = 264 Words (256+8)
x16 DEVICES
8032
4016
2008
1004
Min
Words
Words
8
8
SOFTWARE ALGO-
16 bits
16 bits
section for
8192
4096
2048
1024
Max
AI07587
15/56