M45PE80-VMN6TP NUMONYX, M45PE80-VMN6TP Datasheet - Page 46

• Manufacturer Part Number: M45PE80-VMN6TP
• Description: IC FLASH 8MBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SOIC N
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 16
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE80-VMN6TPCT

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Reference
Revision history
Table 22.
05-May-2003
28-May-2004
10-May-2005
10-Feb-2003
26-Nov-2003
14-Feb-2006
02-Apr-2003
08-Apr-2003
04-Jun-2003
23-Jan-2004
4-Oct-2005
AN1995: Serial Flash Memory Device Marking.
Date
Document revision history
Version
1.0
1.1
1.2
1.3
1.4
2.0
3.0
4.0
5.0
6.0
7
Document written
VFQFPN8 (MLP) package added
Document promoted to Product Preview
Document promoted to Preliminary Data
Description corrected of entering Hardware Protected mode (W must be
driven, and cannot be left unconnected). Document Revision History for
05-May-2003 corrected.
V
contents, SO16 package, warning about exposed paddle on MLP8, and
Pb-free options added. Change of naming for VDFPN8 package.
Document promoted to full datasheet
SO16 pin-out corrected
Soldering temperature information clarified for RoHS compliant devices.
Device Grade clarified
SO16 wide package replaced by SO8 wide package.
Active Power, Stand-by Power and Deep Power-Down
Identification
Power-down (RDP)
Table 21: Ordering information scheme
Figure 22: Output timing
Added
modify
Program (PP)
Page Program instructions. Updated I
characteristics. Updated
information added.
X process technology added (see
Reset timings for U process technology devices
timings for X process technology
VFQFPN8, MLP silhouette modified
Table 7: Absolute maximum
Table 5: Status Register Format
to
under
IO
Section 6.4: Read Status Register
(min) extended to –0.6V, and t
Plating Technology
Table 12: AC characteristics (33 MHz
data,
A fast way to modify
(RDID),
sections updated to explain optimal use of Page Write and
descriptions updated.
Deep Power-down
updated.
Table 21: Ordering information scheme
in
ratings.
Table 21: Ordering information
Changes
moved from
devices). MLP package renamed as
PP
data,
Section 2.5: Reset
(typ) improved to 1.2ms. Table of
on page
(RDSR). Blank option removed
CC3
Page Write (PW)
updated.
(DP), and
values in
Section 4.7: Status Register
operation).
1. T
and
LEAD
Release from Deep
Table 11: DC
Table 15: Reset
(Reset),
removed from
modes,
An easy way to
and
scheme.
Page
Table 14:
Read
RoHS