W9425G6EH-5 Winbond Electronics, W9425G6EH-5 Datasheet
W9425G6EH-5
Specifications of W9425G6EH-5
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W9425G6EH-5 Summary of contents
Page 1
... Burst Termination .............................................................................................................................13 7.7 Refresh Operation ............................................................................................................................13 7.8 Power Down Mode ...........................................................................................................................14 7.9 Input Clock Frequency Change during Precharge Power Down Mode ............................................14 7.10 Mode Register Operation .................................................................................................................14 7.10.1 Burst Length field (A2 to A0) ................................................................................................14 7.10.2 Addressing Mode Select (A3)...............................................................................................15 W9425G6EH Publication Release Date:Dec. 03, 2008 - 1 - Revision A08 ...
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... Command Input Timing ....................................................................................................................36 11.2 Timing of the CLK Signals ................................................................................................................36 11.3 Read Timing (Burst Length = 4) .......................................................................................................37 11.4 Write Timing (Burst Length = 4) .......................................................................................................38 11.5 DM, DATA MASK (W9425G6EH).....................................................................................................39 11.6 Mode Register Set (MRS) Timing.....................................................................................................40 11.7 Extend Mode Register Set (EMRS) Timing ......................................................................................41 11.8 Auto-precharge Timing (Read Cycle ..................................................................................42 11.9 Auto-precharge Timing (Read cycle 2), continued ...
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... Precharged/Active Power Down Mode Entry and Exit Timing ..........................................................51 11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing.................................51 11.26 Self Refresh Entry and Exit Timing...................................................................................................52 12. PACKAGE SPECIFICATION .......................................................................................................................53 12.1 TSOP 66 lI – 400 mil ........................................................................................................................53 13. REVISION HISTORY ...................................................................................................................................54 W9425G6EH Publication Release Date:Dec. 03, 2008 - 3 - Revision A08 ...
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... SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. W9425G6EH delivers a data bandwidth 500M words per second (-4). To fully comply with the personal computer industrial standard, W9425G6EH is sorted into the following speed grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the DDR500/CL3 and CL4 specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I grade which is guaranteed to support -40° ...
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... Self-Refresh Current DD6 MIN./MAX. Min Max. Min 2.5 Max. Min Max Min Max Min Min Max. 110 mA Max. 150 mA Max. 210 mA Max. 210 mA Max. 190 mA Max Publication Release Date:Dec. 03, 2008 - 5 - W9425G6EH -4 -5/-5I -6/-6I - 7 110 mA 110 mA 150 mA 150 mA 180 mA ...
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... DQ5 DQ6 V SSQ DQ7 NC V DDQ LDQS LDM WE CAS RAS CS NC BA0 BA1 A10/ W9425G6EH DQ15 64 V SSQ 63 DQ14 62 DQ13 61 V DDQ 60 DQ12 59 DQ11 58 V SSQ 57 DQ10 56 DQ9 55 V DDQ 54 DQ8 SSQ 51 UDQS REF UDM 47 46 CLK 45 CLK CKE A12 41 A11 40 ...
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... Separated power from V I/O Buffer improve noise. Ground for I/O Separated ground from V Buffer improve noise. (NC pin should be connected to GND or No connection No Connection floating W9425G6EH DESCRIPTION ) define the command CS , used for output buffer used for output buffer Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... CELL ARRAY BANK #0 SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 8192 * 512 * W9425G6EH COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ BUFFER DQ15 UDQS COLUMN DECODER CELL ARRAY BANK #3 SENSE AMPLIFIER Publication Release Date:Dec ...
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... Enable DLL . DDQ and V TT MRS PREA AREF 2 Clock min 200 Clock min. DLL reset with A8 = High Initialization sequence after power- W9425G6EH . REF AREF MRS t RFC 2 Clock min. t RFC Disable DLL reset with A8 = Low Publication Release Date:Dec. 03, 2008 Revision A08 ANY CMD ...
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... Read with Auto-precharge Command ( RAS = "H", CAS = ”L” ”H”, BA0, BA1 = Bank, A10 = ”H” Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation. W9425G6EH Publication Release Date:Dec. 03, 2008 - 10 - Revision A08 ...
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... BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO CK - (BL/ W9425G6EH Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... Refer to the diagrams for Read operation. (maximum). To allow for improved REFI . REFI because time is required for the completion of any internal refresh in from the Bank Activate command, the data is read out sequentially W9425G6EH Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... In Self Refresh mode, all input/output buffers are disabled, from the bank activate command. The input data is latched RCD from the bank activate command. RAS(max) . RFC Publication Release Date:Dec. 03, 2008 - 13 - W9425G6EH . Therefore, each RAS (max) Revision A08 ...
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... Burst Length field (A2 to A0) This field specifies the data length for column access using the pins and sets the Burst Length and 8 words BURST LENGTH 0 Reserved 1 2 words 0 4 words 1 8 words x Reserved Publication Release Date:Dec. 03, 2008 - 14 - W9425G6EH Revision A08 ...
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... A0) not carried from words (address bit A0, A1) Not carried from words (address bits A2, A1 and A0) Not carried from Addressing Sequence of Interleave Mode ACCESS ADDRESS - 15 - W9425G6EH BURST LENGTH BURST LENGTH 2 words 4 words 8 words Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... The 100%, 60% and 30% or matched impedance driver strength are required Extended Mode Register Set (EMRS) as the following CAS LATENCY A12-A0 Regular MRS Cycle Extended MRS Cycle Reserved DLL Enable Disable A1 BUFFER STRENGTH Publication Release Date:Dec. 03, 2008 - 16 - W9425G6EH Reserved Reserved Reserved 2.5 Reserved 100% Strength 60% Strength Reserved 30% Strength Revision A08 ...
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... Test mode entry bit (A7) This bit is used to enter Test mode and must be set to "0" for normal operation. • Reserved bits (A9, A10, A11,A12) These bits are reserved for future operations. They must be set to "0" for normal operation. W9425G6EH Publication Release Date:Dec. 03, 2008 - 17 - Revision A08 ...
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... CKE signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BA0, BA1 signals. 4. LDM, UDM (W9425G6EH). 5. Power Down Mode can not entry in the burst cycle. BA0, (4) CKEn-1 CKEn ...
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... BST BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA BA, RA ACT L BA, A10 PRE/PREA X AREF/SELF L Op-Code MRS/EMRS - 19 - W9425G6EH ACTION NOP NOP ILLEGAL ILLEGAL Row activating NOP Refresh or Self refresh Mode register accessing NOP NOP Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ...
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... BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 20 - W9425G6EH ACTION NOTES Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ...
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... READ/WRIT X ACT/PRE/PREA X AREF/SELF/MRS/EMRS X DSL X NOP L X BST X READ/WRIT ACT/PRE/PREA/ARE X F/SELF/MRS/EMRS W9425G6EH ACTION NOTES NOP->Row active after t WR NOP->Row active after t WR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Enter precharge after t WR NOP->Enter precharge after t WR ILLEGAL ...
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... Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table - 22 - W9425G6EH ACTION NOTES XSNR XSNR IS Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... IDLE PDEX ACT PDEX PD ROW ACTIVE Write Read Read A Write A Read A PRE PRE PRE PRE CHARGE PRE - 23 - W9425G6EH SELF REFRESH SREFX AUTO REFRESH PD POWER DOWN BST Read Read Read Read A Read A Automatic Sequence Command Sequence Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... V 0. DDQ V - 0.04 V REF V + 0.15 REF -0.3 -0.3 0. 0.31 REF - 0 0.2 DDQ 0.2 DDQ +1.5V with a pulse width < W9425G6EH RATING UNIT -0 0.3 V DDQ -0 °C - °C -55 ~ 150 °C 260 ° MAX. UNIT NOTES 2.5 2.7 V 2.6 2.7 V 2.5 2 ...
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... OUT (DC) DDQ OUT MIN. 2.0 2.0 4.0 - < Pin 0V < V < DD REF IN < OUT DDQ , min. V REF TT , max REF TT , min. V REF min. V REF TT , max REF W9425G6EH DELTA MAX. (MAX.) 3.0 0.5 3.0 0.25 5.0 0.5 1.5 - UNIT MIN. MAX µ µA V +0. -0. - ...
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... IH IH min or Vin < V max for DQ min; All Banks Idle; CKE min CK CK min; CKE > V min; One max min; DQ, DM RAS CK CK min 0mA OUT min RFC = 3; RCD - 26 - W9425G6EH MAX. UNIT -4 -5/-5I -6/-6I 110 110 110 mA 150 150 150 210 ...
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... CH -0.5 -0.5 0.9 1.1 0.9 0.4 0.6 0.4 0.4 0.4 0.4 0.4 1.75 1.75 0.35 0.35 0.35 0.35 0.2 0.2 0.2 0 Publication Release Date:Dec. 03, 2008 - 27 - W9425G6EH -6/-6I UNIT NOTES MAX. MIN. MAX 70000 42 100000 7 0.7 -0.7 0.7 16 0.6 -0.6 0.6 ...
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... SYMBOL REF (AC) V OTR Publication Release Date:Dec. 03, 2008 - 28 - W9425G6EH -6/-6I UNIT NOTES MAX. MIN. MAX. 0.25 0.6 0.4 0 1.25 0.75 1.25 0.75 19, 21-23 0.75 19, 21-23 0.8 20-23 0.8 20-23 2.2 nS 0.7 -0.7 0.7 0.7 -0.7 ...
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... TT . REF and V .Transition (rise and fall) of input signals have a fixed IH min(AC) IL max(AC) contains more than one decimal place, the result is rounded CLK )}/ W9425G6EH VTT 50 Ω 30pF Timing Reference Load Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. (23) Slew Rate is measured between ICK ICK V V ISO(min) ISO(max) (ac) and V (ac W9425G6EH ICK ID(AC) Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... +50 0 +100 0 Δt Δ +75 0 +150 0 Δt Δ +50 0 +100 0 TYPICAL MINIMUM RANGE (V/NS) (V/NS) 1.2 ~ 2.5 0.7 1.2 ~ 2.5 0 W9425G6EH DDR333 UNIT NOTES MIN. MAX. 4.0 0.5 4.0 V/ UNIT NOTES UNIT NOTES UNIT NOTES MAXIMUM NOTES (V/NS Publication Release Date:Dec ...
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... Figure 3: Address and Control AC Overshoot and Undershoot Definition DDR500 DDR400 MIN. MAX. MIN. MAX. 0.67 1.5 0.67 DDR500 1.5 V 1.5 V 3.0 V-nS 3.0 V-nS Overshoot Time (nS W9425G6EH DDR333 NOTES MIN. MAX. 1.5 0.67 1 SPECIFICATION DDR400 DDR333 1.5 V 1.5 V 1.5 V 1.5 V 3.0 V-nS 3.6 V-nS 3 ...
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... Figure 4: DQ/DM/DQS AC Overshoot and Undershoot Definition DDR500 1.2 V 1.2 V 1.44 V-nS 1.44 V-nS Overshoot Time (nS W9425G6EH SPECIFICATION DDR400 DDR333 1.2 V 1.2 V 1.2 V 1.2 V 1.44 V-nS 2.25 V-nS 1 ...
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... Verified under typical conditions for qualification purposes. Test point 50 Ω VSSQ /2 - 320 mV ± 250 mV) DDQ /2 + 320 mV ± 250 mV) DDQ = nominal, typical process DDQ = minimum, slow-slow process DDQ = maximum, fast-fast process DDQ Publication Release Date:Dec. 03, 2008 - 34 - W9425G6EH Revision A08 ...
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... DQ, DM, and DQS slew similarly for rising transitions. IL(AC) IH(DC) IL(DC) and t in the case where the I/O slew rate is below 0.5 V/nS. The W9425G6EH and t of 100 IH(AC) IL(AC) Publication Release Date:Dec. 03, 2008 Revision A08 IH(DC) ...
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... TIMING WAVEFORMS 11.1 Command Input Timing CLK CLK CS RAS CAS WE A0~A12 BA0,1 11.2 Timing of the CLK Signals CLK CLK CLK CLK Refer to the Command Truth Table W9425G6EH IH(AC) V IL(AC Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... CLK READ CMD ADD Col CAS Latency = 2 Hi-Z DQS Output Hi-Z (Data) CAS Latency = 3 Hi-Z DQS Hi-Z Output (Data) Notes: The correspondence of LDQS, UDQS to DQ. (W9425G6EH) LDQS DQ0~7 UDQS DQ8~ DQSCK t DQSCK t RPRE Preamble t t DQSQ QH QA0 QA1 DA0 DA1 t AC ...
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... DSH DSS DSH DSS DQSH DQSL DQSH WPST Postamble DA0 DA1 DA2 DA3 DA0 DA1 DA2 DA3 DSH DSS DSH DSS DQSL DQSH WPST DQSH Postamble DA0 DA1 DA2 DA3 DA0 DA1 DA2 DA3 - 38 - W9425G6EH Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... DM, DATA MASK (W9425G6EH W9425G6EH Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... CAS Latency A6 A7 Reserved "0" A8 DLL Reset "0" A9 A10 "0" Reserved A11 "0" A12 "0" BA0 "0" Mode Register Set or Extended Mode "0" BA1 Register Set * "Reserved" should stay "0" during MRS cycle. W9425G6EH t MRD NEXT CMD Burst Length Sequential Reserved ...
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... EMRS cycle t MRD NEXT CMD DLL Switch A0 Enable 0 Disable Buffer Strength 0 0 100% Strength 1 0 60% Strength 0 1 Reserved 1 1 30% Strength BA0 BA1 MRS or EMRS 0 0 Regular MRS cycle 1 Extended MRS cycle Publication Release Date:Dec. 03, 2008 - 41 - W9425G6EH Revision A08 ...
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... Notes: CL=2 shown; same command operation timing with CL = 2,5 and CL=3 In this case, the internal precharge operation begin after BL/2 cycle from READA command. AP Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command RAS READA READA READA W9425G6EH tRP ACT ACT ACT Q3 ...
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... Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command. – (BL/2) × t RAS (min RAS READA Q0 Q1 READA READA W9425G6EH t RP ACT AP AP ACT Q3 AP ACT (min) has command. RAS Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... BL=2 WRITA CMD DQS BL=4 WRITA CMD DQS BL=8 WRITA CMD DQS The Write with Auto-precharge command cannot be interrupted by any other command. AP Represents the start of internal precharging . t DAL AP t DAL W9425G6EH ACT ACT t DAL AP ACT Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... CLK READ CMD CAS Latency = 2 DQS DQ CAS Latency = 3 DQS DQ READ A READ RCD CCD CCD COl,Add,A Col,Add,B Col,Add,C BST CAS Latency CAS Latency W9425G6EH READ C READ D READ CCD CCD Col,Add,D Col,Add,E QA0 QA1 QB0 QB1 QC0 Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... Read Interrupted by Write & BST ( CLK CLK CAS Latency = 2 READ CMD DQS DQ Q0 Burst Read cycle must be terminated by BST Command to avoid I/O conflict. 11.14 Read Interrupted by Precharge ( READ Latency = Latency = BST WRIT Latency Latency W9425G6EH Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... WRIT B WRIT CCD CCD COl. Add. A Col.Add.B Col. Add. C DA0 DA1 DB0 READ t WTR Data masked by READ command, DQS input ignored W9425G6EH WRIT D WRIT CCD CCD Col. Add. D Col. Add. E DB1 DC0 DC1 DD0 DD1 Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... CLK CLK WRIT CMD DQS 11.18 Write Interrupted by Precharge ( CLK CLK WRIT CMD DQS READ t WTR D2 D3 Data must be masked by DM PRE ACT Data must be Data masked by PRE command, masked by DM DQS input ignored W9425G6EH Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... RAS(b) Preamble CL(a) APa t RC(b) t RC(a) ACTb READAa READAb t RCD(a) t RAS(a) t RCD(b) t RAS(b) Preamble CL(a) CL(b) Q0a Q1a APa - 49 - W9425G6EH t RRD ACTa ACTb t RP(b) Postamble Preamble Postamble CL(b) Q0a Q1a Q0b Q1b APb t RRD ACTa ACTb t RP(a) t RP(b) Postamble Q2a Q3a ...
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... READ Aa/b/c/d : Read w ith Auto Pre. bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d 11.22 4 Bank Interleave Read Operation ( ith C( ACTc R EADAa ACTd ( AS( ( AS(b) C L(a) APa W9425G6EH EAD READ D(c) t RAS( (d) t RAS(d) Pream ble Postam ble Pream ble CL( Q0b Q 1b APb Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... Minmum 2 clocks required before changing frequency AREF NOP t RFC Entry NOP Frequency Change Occurs here Stable new clock before power down exit - 51 - W9425G6EH AREF CMD NOP t RFC t IS Exit NOP CMD NOP DLL NOP NOP NOP CMD RESET t IS 200 clocks Publication Release Date:Dec ...
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... PREA NOP SELF t RP Entry SELF Entry Note: If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit SELEX Exit t XSNR t XSRD SELFX NOP ACT NOP READ Exit Publication Release Date:Dec. 03, 2008 - 52 - W9425G6EH NOP CMD NOP Revision A08 ...
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... PACKAGE SPECIFICATION 12.1 TSOP 66 lI – 400 mil W9425G6EH Publication Release Date:Dec. 03, 2008 Revision A08 ...
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... AC characteristics Remove -75 grade parts 31 Revise -4 speed grade AC parameter tWTR from 1 tCK to 2 tCK Add -5I and -6I industrial grade parts 26, 27 Add 30% driver strength and -4 grade parts add to support CL4 27, 40, 41 Important Notice - 54 - W9425G6EH DESCRIPTION Publication Release Date:Dec. 03, 2008 Revision A08 ...