MD2534-D1G-X-P SanDisk, MD2534-D1G-X-P Datasheet - Page 26

• Manufacturer Part Number: MD2534-D1G-X-P
• Description: IC MDOC H3 1GB FBGA
• Manufacturer: SanDisk

Specifications of MD2534-D1G-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (128M x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 115-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.2
3.2.1
The host interface block provides an easy-to-integrate NOR-like (also SRAM and EEPROM-like)
interface to mDOC H3, enabling various CPU interfaces, such as a local bus, ISA bus, NOR
interface, SRAM interface, EEPROM interface or any other compatible interface. In addition, the
EEPROM-like interface enables direct access to the Programmable Boot Block to permit XIP
(Execute-In-Place) functionality during system initialization.
A1-A16 address lines enable access to the mDOC H3 128KB memory window. When migrating
from mDOC G3/G4/H1 without changing the PCB, thus using only A1-A12 address lines, mDOC
H3 exports 8KB memory window, like in mDOC G3/G4 and H1.
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and
write cycles. A write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly,
a read cycle occurs while both the CE# and OE# inputs are asserted. Note that mDOC H3 does
not require a clock signal. It features a unique analog static design, optimized for minimal power
consumption. The CE#, WE# and OE# signals trigger the controller (e.g., system interface block,
bus control and data pipeline) and flash access.
The Reset-In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase.
WARM_RST# signal (warm reset) is used to reset the Host IF and enter a predefined reset
scenario of mDOC H3.
The Interrupt Request (IRQ#) signal is used to indicate completion of operations. Using this
signal frees the CPU to run other tasks, continuing read/write operations with mDOC H3 only
after the IRQ# signal has been asserted and an interrupt handling routine (implemented in the OS)
has been called to return control to the DOC driver.
The DMARQ# output is used to control DMA operations, and the CLK input is used to support
Burst operation when reading flash data. See Section 10.3 for further information.
3.2.2
In this configuration, the address and data signals are multiplexed. The AVD# input is driven by
the host AVD# signal, and the D[15:0] balls, used for both address inputs and data, are connected
to the host AD[15:0] bus. While AVD# is asserted, the host drives AD[15:0] with bits [16:1] of
the address.
This interface is automatically used when a falling edge is detected on AVD#. This edge must
occur after RSTIN# is de-asserted and before the first read or write cycle to the controller.
26
Host Interface
Standard (NOR-Like) Interface
Multiplexed Interface
• Flash Agent – Provides High level Flash management functions and sequences for
• Flash IF – Physical interface to the Flash Media.
• Power and Timing – Analog and clock circuits to provide power and timing for the
• Embedded CPU – Runs Embedded TrueFFS SW and mDOC H3 Controller
Flash control and error condition handling.
H3 controller and flash.
operating SW.
Data Sheet (Preliminary) Rev. 0.2
mDOC H3 Embedded Flash Drive
92-DS-1205-10