PCA8534AH/Q900/1,5 NXP Semiconductors, PCA8534AH/Q900/1,5 Datasheet - Page 17

• Manufacturer Part Number: PCA8534AH/Q900/1,5
• Description: IC LCD DRIVER 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCA8534AH/Q900/1,5

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 80µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 60
• Maximum Clock Frequency: 3046 Hz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 95 C
• Attached Touch Screen: No
• Maximum Supply Current: 20 uA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5110-2

NXP Semiconductors
PCA8534A_2
Product data sheet
7.12 Subaddress counter
7.11 Data pointer
The following applies to
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
If an I
The data pointer should be re-written prior to further RAM accesses.
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed only when the contents of the subaddress counter agree with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see
and the hardware subaddress do not match then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
In cascaded applications each PCA8534A in the cascade must be addressed separately.
Initially, the first PCA8534A is selected by sending the device-select command matching
the first device's hardware subaddress. Then the data pointer is set to the preferred
display RAM address by sending the load-data-pointer command.
Once the display RAM of the first PCA8534A has been written, the second PCA8534A is
selected by sending the device-select command again. This time however the command
matches the second device's hardware subaddress. Next the load-data-pointer command
is sent to select the preferred display RAM address of the second PCA8534A.
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Static mode: the eight transmitted data bits are placed in row 0 to eight successive
display RAM addresses.
1:2 multiplex mode: the eight transmitted data bits are placed in row 0 and 1 to four
successive display RAM addresses.
1:3 multiplex mode: the eight transmitted data bits are placed in row 0, 1, and 2 to
three successive addresses. However, bit 2 of the third address is left unchanged.
This last bit can, if necessary, be controlled by an additional transfer to this address
but avoid overriding adjacent data because full bytes are always transmitted.
1:4 multiplex mode: the eight transmitted data bits are placed in row 0, 1, 2, and 3 to
two successive display RAM addresses.
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
2
C-bus data access is terminated early then the state of the data pointer is unknown.
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 1 June 2010
Figure
Figure
10:
10.
Table
13). If the content of the subaddress counter
Universal LCD driver for low multiplex rates
Table
12). Following this command,
PCA8534A
© NXP B.V. 2010. All rights reserved.
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