PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 37
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
PCF8534AHL/1,518
Manufacturer Part Number
PCF8534AHL/1,518
Description
IC LCD DISPLAY DRVR 60SEG 80LQFP
Manufacturer
NXP Semiconductors
Specifications of PCF8534AHL/1,518
Package / Case
80-LQFP
Display Type
LCD
Configuration
60 Segment
Interface
I²C
Current - Supply
8µA
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Digits
30
Number Of Segments
240
Maximum Clock Frequency
400 KHz
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 85 C
Maximum Supply Current
50 mA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Digits Or Characters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-5058-2
935289852518
935289852518
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PCF8534AHL/1,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 11.
T
with respect to ground; positive currents flow in the IC; typical values are given at V
[1]
[2]
[3]
UJA1076_2
Product data sheet
Symbol
Oscillator
f
osc
vj
=
A system reset will be performed if the watchdog is in Window mode and is triggered less than t
period (or in the first half of the watchdog period).
The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see
Window mode only.
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
−
trig(wd)2
40 °C to +150
after the start of the watchdog period (watchdog overflows).
Dynamic characteristics
Parameter
oscillator frequency
°
C; V
BAT
Fig 15. Timing test circuit for CAN transceiver
= 4.5 V to 28 V; V
…continued
C RXDC
All information provided in this document is subject to legal disclaimers.
BAT
Conditions
> V
Rev. 02 — 27 May 2010
RXDC
TXDC
V1
; V
BAT
SBC
GND
BAT
> V
V2
; R
CANH
CANL
trig(wd)1
(CANH-CANL)
High-speed CAN core system basis chip
, but not more than t
R CANH − R CANL
BAT
= 45
= 14 V; unless otherwise specified.
Ω
trig(wd)1
015aaa079
to 65
Min
460.8
trig(wd)2
after the start of the watchdog
Ω
; all voltages are defined
C CANH − C CANL
Table
, after the start of the
Typ
512
UJA1076
© NXP B.V. 2010. All rights reserved.
4); valid in watchdog
Max
563.2
37 of 47
Unit
kHz