pcf8534 NXP Semiconductors, pcf8534 Datasheet
pcf8534
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pcf8534 Summary of contents
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... Rev. 00.05 — 20 February 2007 1. General description The PCF8534 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and segments and can easily be cascaded for larger LCD applications ...
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... Ordering information Table 1. Ordering information Type number Topside Package mark Name PCF8534H PCF8534H LQFP80 PCF8534_0 Preliminary datasheet Universal LCD driver for low multiplex rates Description plastic, low profile, quad flat package; 80 leads; body 1.4 mm SOT315-1 Rev. 00.05 — 20 February 2007 PCF8534 Version © ...
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... Block diagram Fig 1. PCF8534 block diagram ...
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... S41 11 S42 12 S43 13 14 S44 S45 15 S46 16 S47 17 18 S48 19 S49 S50 20 Fig 2. PCF8534 pin configuration Table 2. Pin PCF8534_0 Preliminary datasheet Universal LCD driver for low multiplex rates PCF8534 Pin allocation table Symbol S31 S32 S33 S34 ...
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... BP1 BP2 BP3 n.c. n.c. n.c. n.c. SDA SCL CLK Pin description Pin Description external clock input / output 41 supply voltage 42 cascade synchronization input / output Rev. 00.05 — 20 February 2007 PCF8534 Pin Symbol S10 61 ...
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... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCF8534 depend on the number of active backplane outputs required; a selection of display configurations is given in All of the display configurations given in ...
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... MICRO- CONTROLLER V SS Fig 3. Typical system configuration 6.1 Power-on-reset At power on the PCF8534 resets to a starting condition as follows: 1. All backplane outputs are set All segment outputs are set The drive mode ‘ multiplex with 4. Blinking is switched off. 5. Input and output bank selectors are reset (as defined in Table 7 old datasheet). ...
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... OFF ms ---------------------- - configuration static 0 ⁄ 1 0.354 2 ⁄ 1 0.333 3 ⁄ 1 0.333 3 ⁄ 1 0.333 3 Rev. 00.05 — 20 February 2007 PCF8534 with a defined LCD threshold OFF(rms) . bias are possible but the discrimination and ⎞ for 1:4 multiplex ⎠ = 2.449V ( ) ( ) OFF rms ) = 2.309V ( ) OFF rms ⁄ 1 bias is used. Note: V ...
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... LCD V LCD state −V LCD (b) Resultant waveforms at LCD segment. (t) − (t). sn BP0 = V . LCD (t) − (t). ( BP0 = 0 V. Rev. 00.05 — 20 February 2007 PCF8534 Figure 4. LCD segments state 1 state 2 (on) (off) mgl745 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 6.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8534 allows the use of Figure 6. V state1 V ON(rms) V state2 V OFF(rms) Fig 5. Waveforms for the 1:2 multiplex drive mode with PCF8534_0 Preliminary datasheet Universal LCD driver for low multiplex rates ⁄ ...
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... LCD −2V /3 LCD −V LCD (b) Resultant waveforms at LCD segment. (t) − (t). sn BP0 = 0.745 V . LCD (t) − (t). (sn) BP1 = 0.333 V . LCD Rev. 00.05 — 20 February 2007 PCF8534 T frame LCD segments state 1 state 2 mgl747 ⁄ 1 bias. 3 © NXP B.V. 2007. All rights reserved ...
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... V −V /3 LCD −2V /3 LCD −V LCD (b) Resultant waveforms at LCD segment. (t) − (t). sn BP0 = 0.638 V . LCD (t) − (t). (sn) BP1 = 0.333 V . LCD Rev. 00.05 — 20 February 2007 PCF8534 frame LCD segments state 1 state 2 mgl748 © NXP B.V. 2007. All rights reserved ...
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... LCD 0 V −V /3 LCD −2V /3 LCD −V LCD (b) Resultant waveforms at LCD segment. (t) − (t). sn BP0 = 0.577 V . LCD (t) − (t). (sn) BP1 = 0.333 V . LCD Rev. 00.05 — 20 February 2007 PCF8534 LCD segments state 1 state 2 mgl749 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 6.5 Oscillator 6.5.1 Internal clock The internal logic and the LCD drive signals of the PCF8534 are timed either by the built-in oscillator or from an external clock. When the internal oscillator is used, you must connect pad OSC to V for cascaded PCF8534’s in the system. After power-up, SDA must be HIGH to guarantee that the clock starts ...
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... RAM are time-multiplexed with BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF8534 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands ...
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... The SYNC signal will reset these sequences to the following starting points; bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex and bit 0 for static mode. The PCF8534 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit selected for display instead of the contents of bit 0 ...
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... Blinker The display blinking capabilities of the PCF8534 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating, see An additional feature is for an arbitrary selection of LCD segments to be blinked ...
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LCD segments LCD backplanes a S n+2 b BP0 f S n static e S n n+6 ...
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... Universal LCD driver for low multiplex rates 2 C bus Figure 11. SDA SCL data line stable; data valid S START condition Rev. 00.05 — 20 February 2007 PCF8534 change of data allowed mba607 Figure 12. P STOP condition mbc622 © NXP B.V. 2007. All rights reserved. SDA SCL ...
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... Figure 14. 1 master S START condition 2 C-bus 2 C-bus controller 2 C-bus slave receiver. It does not initiate I 2 C-bus master receiver. The only data output from the PCF8534 are Rev. 00.05 — 20 February 2007 PCF8534 MASTER MASTER TRANSMITTER/ TRANSMITTER RECEIVER 2 C-bus is not acknowledge acknowledge ...
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... C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8534. The least significant bit of the slave address that a PCF8534 will respond to is defined by the level tied at its input SA0. The PCF8534 is a write only device and will not respond to a read access. Therefore, two types of PCF8534 can be distinguished on the same ...
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R slave address control byte EXAMPLES a) transmit two bytes of RAM data ...
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... NXP Semiconductors 7.9 Command decoder The command decoder identifies command bytes that arrive on the I commands available to the PCF8534 are defined in Table 8. Definition of PCF8534 commands Command OPCODE Mode set Load data pointer Device select ...
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... PCF8534 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. 7.11 Cascaded operation In large display configurations PCF8534’s can be distinguished on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable ...
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... SA0 levels are cascaded). SYNC is organized as an input / output pad; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF8534 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost restored by the first PCF8534 to assert SYNC ...
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... NXP Semiconductors handbook, full pagewidth V LCD HOST MICRO- PROCESSOR/ MICRO- CONTROLLER V SS Fig 17. Cascaded PCF8534 configuration PCF8534_0 Preliminary datasheet Universal LCD driver for low multiplex rates LCD SDA SCL 60 segment drives SYNC PCF8534 CLK OSC SA0 ...
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... NXP Semiconductors Fig 18. Synchronization of the cascade for various PCF8534 drive modes PCF8534_0 Preliminary datasheet Universal LCD driver for low multiplex rates frame frame BP0 SYNC (a) static drive mode. BP1 (1/2 bias) BP1 (1/3 bias) SYNC ( multiplex drive mode. BP2 SYNC ( multiplex drive mode. ...
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... AMB Conditions f = 1536 Hz CLK f = 1536 Hz CLK Rev. 00.05 — 20 February 2007 PCF8534 Min Max Unit −0.5 +6.5 V −50 +50 mA − 0 −50 +50 mA −50 +50 mA − ...
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... LCD LCD external clock with 50% duty factor − +85°C; unless otherwise specified AMB Conditions LCD Rev. 00.05 — 20 February 2007 PCF8534 Min Typ Max − − − [ 1.0 1.3 1.6 −100 - +100 −100 ...
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... Universal LCD driver for low multiplex rates − +85°C; unless otherwise specified AMB Conditions Ω 6.8 SYNC V DD (2%) Ω 3.3 k SDA, CLK 0.5V DD SCL (2 BP0 to BP3, and S0 to S59 V SS Rev. 00.05 — 20 February 2007 PCF8534 Min Typ Max Unit μs 0 μs 0 μs 1 μs 0 μ ...
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... Universal LCD driver for low multiplex rates 1/ f CLK t CLKH t CLKL d(p)(SYNC) t SYNCL t PLCD t t BUF LOW t HD;STA SU;STA C-bus timing waveforms Rev. 00.05 — 20 February 2007 PCF8534 0.7V DD 0.3V DD 0. d(p)(SYNC) 0 0.5 V MGL761v03 HD;DAT t SU;DAT HIGH © NXP B.V. 2007. All rights reserved ...
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... scale (1) ( 0.18 12.1 12.1 14.15 14.15 0.5 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC JEITA MS-026 Rev. 00.05 — 20 February 2007 PCF8534 detail (1) ( 0.75 1.45 1.45 1 0.2 0.15 0.1 0.30 1.05 1.05 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-25 © NXP B.V. 2007. All rights reserved. ...
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... Universal LCD driver for low multiplex rates LCD LCD Rev. 00.05 — 20 February 2007 PCF8534 SCL SDA V LCD MGL760v02 © NXP B.V. 2007. All rights reserved ...
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... Solder bath specifications, including temperature and impurities PCF8534_0 Preliminary datasheet Universal LCD driver for low multiplex rates Rev. 00.05 — 20 February 2007 PCF8534 © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 24. Rev. 00.05 — 20 February 2007 PCF8534 Figure 24) than a PbSn process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2007. All rights reserved. ...
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... PCF8534_0 Preliminary datasheet Universal LCD driver for low multiplex rates maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature Rev. 00.05 — 20 February 2007 PCF8534 peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved ...
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... Data sheet status Preliminary 21: clock oscillator frequency (added external) Objective 1:added column for ‘Topside mark’ 8.1: added ESD values. Objective Objective Rev. 00.05 — 20 February 2007 PCF8534 Change notice Supersedes PCF8534_00.03 PCF8534_00.02 PCF8534_00.01 first release © NXP B.V. 2007. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 00.05 — 20 February 2007 PCF8534 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors PCF8534_0 Preliminary datasheet Universal LCD driver for low multiplex rates Notes Rev. 00.05 — 20 February 2007 PCF8534 © NXP B.V. 2007. All rights reserved ...
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... Blinker Application design-in information . . . . . . . . . 19 2 7.1 Characteristics of the I C bus . . . . . . . . . . . . . 19 7.2 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 START and STOP conditions . . . . . . . . . . . . . 19 7.4 System configuration . . . . . . . . . . . . . . . . . . . 19 7.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 PCF8534 I2C-bus controller . . . . . . . . . . . . . . 20 7.7 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.8 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 7.9 Command decoder . . . . . . . . . . . . . . . . . . . . . 23 7.10 Display controller . . . . . . . . . . . . . . . . . . . . . . 24 7.11 Cascaded operation . . . . . . . . . . . . . . . . . . . . 24 8 Limiting values 8.1 ESD values . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Static characteristics Dynamic characteristics ...