pcf8534 NXP Semiconductors, pcf8534 Datasheet - Page 14

• Manufacturer Part Number: pcf8534
• Description: Universal Driver Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8534_0
Preliminary datasheet
6.5.1 Internal clock
6.5.2 External clock
6.5 Oscillator
6.6 Timing
6.7 Display register
6.8 Segment outputs
6.9 Backplane outputs
The internal logic and the LCD drive signals of the PCF8534 are timed either by the
built-in oscillator or from an external clock. When the internal oscillator is used, you must
connect pad OSC to V
for cascaded PCF8534’s in the system. After power-up, SDA must be HIGH to guarantee
that the clock starts.
The condition for external clock is made by tying pad OSC to V
the external clock input.
The clock frequency (f
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state.
The timing of the PCF8534 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8534’s in the system. The timing also generates the LCD
frame frequency which it derives as an integer division of the clock frequency
(see
frequency applied to pad CLK when an external clock is used.
The display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs and one column of the display RAM.
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data resident in the display latch. When less than
60 segment outputs are required the unused segment outputs must be left open-circuit.
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required the
unused outputs can be left open-circuit. In the 1:3 multiplex drive mode BP3 carries the
same signal as BP1, therefore these two adjacent outputs can be tied together to give
enhanced drive capabilities. In the 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3
respectively carry the same signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is carried by all four backplane
outputs and they can be connected in parallel for very high drive requirements.
Table
6). The frame frequency is a fixed division of the internal clock or of the
Rev. 00.05 — 20 February 2007
CLK
SS
. In this event, the output from pad CLK provides the clock signal
) determines the LCD frame frequency.
Universal LCD driver for low multiplex rates
DD
; pad CLK then becomes
PCF8534
© NXP B.V. 2007. All rights reserved.
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