PCF8534AH/1,518 NXP Semiconductors, PCF8534AH/1,518 Datasheet - Page 19

• Manufacturer Part Number: PCF8534AH/1,518
• Description: IC LCD DVR UNVRSL LOW-MUX 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AH/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Details
• Other names: 935284829518; PCF8534AH/1-T; PCF8534AH/1-T

NXP Semiconductors
PCF8534A_3
Product data sheet
8.1.1.1 START and STOP conditions
8.1.2 System configuration
8.1.3 Acknowledge
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in
A device generating a message is a ‘transmitter’ and a device receiving a message is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’. The system configuration is illustrated in
Figure
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse.
Fig 12. Bit transfer
Fig 13. Definition of START and STOP conditions
Fig 14. System configuration
SCL
SDA
SDA
SCL
14.
TRANSMITTER/
RECEIVER
MASTER
START condition
SDA
SCL
S
Rev. 03 — 10 November 2008
RECEIVER
SLAVE
data valid
data line
stable;
TRANSMITTER/
RECEIVER
Universal LCD driver for low multiplex rates
SLAVE
change
allowed
of data
TRANSMITTER
MASTER
STOP condition
Figure
mba607
PCF8534A
P
TRANSMITTER/
© NXP B.V. 2008. All rights reserved.
13.
RECEIVER
MASTER
mbc622
mga807
SDA
SCL
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