pcf8534a NXP Semiconductors, pcf8534a Datasheet
pcf8534a
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pcf8534a Summary of contents
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... The PCF8534A is a peripheral device which interfaces to almost any LCD with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and segments. In addition, the PCF8534A can be easily cascaded for larger LCD applications. The PCF8534A is compatible with most ...
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... V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF8534A PCF8534A_3 Product data sheet Description plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm wire bond die; 76 bonding pads; 2.91 2.62 0.38 mm Marking codes Marking code ...
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... PCF8534AH Top view. For mechanical details, see Figure PCF8534AH/1 pin configuration (SOT315-1) Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates 23. © NXP B.V. 2008. All rights reserved. 60 S10 ...
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... BP1 BP2 75 76 BP3 SDA 1 2 SCL CLK 3 F For mechanical details, see Figure 24. PCF8534AU/DA/1 pin configuration (bare die) Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates PCF8534A-1 Top view C2 43 S30 42 S29 41 S28 40 S27 39 S26 ...
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... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCF8534A depend on the number of active backplane outputs required. Display configuration selection is shown in display configurations can be implemented in the typical system shown in Table 4 ...
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... Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to V power supplies (pins V 7.1 Power-on reset At power-on the PCF8534A resets to a default starting condition: • All backplane outputs are set to V • All segment outputs are set to V • ...
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... Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates and the resulting oper with a defined LCD off(RMS) > oper th 1 bias are possible but the discrimination and 2 for 1:4 multiplex = 1.528 ...
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... V ( (t) V (t). state2 ( BP0 off(RMS) Static drive mode waveforms Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates Figure T fr LCD segments state 1 state 2 (on) (off) mgl745 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8534A allows the use of Figure 7. Fig 6. PCF8534A_3 Product data sheet 1 1 bias LCD BP0 LCD LCD BP1 LCD LCD ...
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... V (t) V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms mgl747 at LCD segment. 1 bias 3 © NXP B.V. 2008. All rights reserved. ...
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... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:3 multiplex drive mode with Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 mgl748 at LCD segment. 1 bias 3 © NXP B.V. 2008. All rights reserved ...
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... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:4 multiplex drive mode with Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates T fr state 1 state 2 mgl749 at LCD segment. 1 bias 3 © NXP B.V. 2008. All rights reserved. LCD segments ...
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... The clock frequency f clk(ext) 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin V output from pin CLK is the clock signal for any cascaded PCF8534A in the system. After power-on, SDA must be HIGH to guarantee that the clock starts. 7.5.2 External clock Connecting pin OSC to V external clock input ...
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... Fig 10. Display RAM bit map When display data is transmitted to the PCF8534A, the display bytes received are stored in the display RAM based on the selected LCD drive mode. Data is stored as it arrives and does not wait for the acknowledge cycle. Depending on the current multiplexer mode data is stored singularly, in pairs, triplets or quadruplets ...
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... C-bus data access terminates early, the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses. PCF8534A_3 Product data sheet Universal LCD driver for low multiplex rates Figure 11: Rev. 03 — 10 November 2008 PCF8534A Figure 11). Once each byte © NXP B.V. 2008. All rights reserved ...
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LCD segments LCD backplanes a S n+2 b BP0 n static n n+6 BP0 1 ...
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... Then the data pointer is set to the preferred display RAM address by sending the load data pointer command. Once the display RAM of the first PCF8534A has been written, the second PCF8534A is selected by sending the device select command again. This time however the command matches the second device's hardware subaddress ...
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... NXP Semiconductors 7.15 Blinker The display blinking capabilities of the PCF8534A are very versatile. The whole display can be blinked at frequencies set by the blink select command (see blinking frequencies are fractions of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating (see Table 7 ...
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... Product data sheet SDA SCL data line stable; data valid S START condition MASTER SLAVE TRANSMITTER/ RECEIVER RECEIVER Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates change of data allowed mba607 Figure P STOP condition SLAVE MASTER TRANSMITTER/ TRANSMITTER RECEIVER 13 ...
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... C-bus 2 C-bus controller 2 C-bus slave receiver. It does not initiate I 2 C-bus master receiver. The only data output from the PCF8534A are which defines the hardware subaddress 0. In multiple device applications using a binary coding scheme so that no two C-bus slave address have the same hardware subaddress. ...
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... Two I C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8534A. The least significant bit of the slave address is bit R/W. The PCF8534A is a write-only device. It will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two displays controlled by PCF8534A can be recognized on the same I • ...
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... B LCD bias configuration 1 0 bias bias 2 Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates A P COMMAND RAM DATA RAM DATA C-bus. There are ...
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... RAM bit 0 1 RAM bit 2 O output bank selection: retrieval of LCD display data 0 RAM bit 0 1 RAM bit 2 Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates …continued Section 7.13 and Section 7.14. 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 ...
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... Only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes. 8.4 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8534A and coordinates their effects. The controller also loads display data into the display RAM as required by the storage order. ...
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... V DD OSC SYNC A0, A1 LCD BP0, BP1, BP2, BP3 LCD S0 to S59 V SS Rev. 03 — 10 November 2008 PCF8534A SCL V SS SDA LCD V SS 001aah615 © NXP B.V. 2008. All rights reserved ...
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... Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. LCD ...
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... V; on pin SDA bpl LCD sgm LCD external clock with 50 % duty factor Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates Min Typ Max 1.8 - 5.5 2.5 - 6 ...
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... Product data sheet = 2 6 +85 C; unless otherwise specified. LCD amb Conditions LCD . Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates Min Typ [1] 960 1536 797 1536 130 - 130 - - ...
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... Product data sheet clk t clk(H) CLK SYNC t PD(SYNC_N BUF LOW t HD;STA C-bus timing waveforms Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates t clk(L) t PD(SYNC_N) t SYNC_NL t PD(drv) 001aah618 HD;DAT t HIGH t SU;STA © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 13. Application information 13.1 Cascaded operation Large display configurations PCF8534As can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable 2 I C-bus slave address (SA0). Table 18. Cluster cascaded PCF8534As are synchronized, they can share the backplane signals from one of the devices in the cascade ...
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... A PCF8534A asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost restored by the first PCF8534A to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal ...
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... NXP Semiconductors Fig 22. Synchronization of the cascade for various PCF8534A drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, the device will not be able to synchronize properly. Table 19 Table 19. Number of devices ...
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... scale (1) ( 0.27 0.18 12.1 12.1 14.15 14.15 0.5 0.13 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates detail 0.75 1.45 1 0.2 0.15 0.1 0.30 1.05 EUROPEAN PROJECTION SOT315 ...
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... F 4 DIMENSIONS (mm are the original dimensions) UNIT max mm nom 0.38 2.91 2.62 min Notes 1. Pad size 2. Passivation opening 3. Marking code OUTLINE VERSION IEC PCF8534AU Fig 24. PCF8534AU die outline PCF8534A_3 Product data sheet D (3) PC8534A 0.5 scale (1) (2) (1) ( ...
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... Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates Description 2 I C-bus serial data input and output 2 I C-bus serial clock input external clock input and output supply voltage cascade synchronization input and output ...
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... Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates Description LCD segment output LCD backplane output Figure 24). © NXP B.V. 2008. All rights reserved ...
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... MOS devices; see JESD625-A and/or IEC61340-5 . PCF8534A_3 Product data sheet REF C1 REF F [1] Alignment mark locations 1387 1335 1345 Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates REF C2 001aai649 1190 1242 1173 Figure 24). © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 17. Packing information Fig 26. Tray details for PCF8534AU/DA/1 Fig 27. Tray alignment for PCF8534AU/DA/1 PCF8534A_3 Product data sheet 1.1 2.1 3.1 1.2 2.2 1 Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates A x.1 E PC8534A-1 001aai650 © NXP B.V. 2008. All rights reserved ...
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... Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates Value 5.5 mm 4.9 mm 3.08 mm 2. ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 28. Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates Figure 28) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Integrated Circuit Liquid Crystal Display Machine Model Random Access Memory Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates peak temperature © NXP B.V. 2008. All rights reserved. time 001aac844 ...
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... Universal LCD driver for low multiplex rates Data sheet status Product data sheet Product data sheet Section 7.10 on page 14 and Section 7.12 on page Section 10 on page 26. Figure 22 on page 32. Product data sheet Rev. 03 — 10 November 2008 PCF8534A Change notice Supersedes - PCF8534A_2 - PCF8534A_1 17 © NXP B.V. 2008. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 10 November 2008 PCF8534A Universal LCD driver for low multiplex rates © NXP B.V. 2008. All rights reserved ...
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... Packing information . . . . . . . . . . . . . . . . . . . . 38 Soldering of SMD packages . . . . . . . . . . . . . . 39 Introduction to soldering Wave and reflow soldering . . . . . . . . . . . . . . . 39 Wave soldering Reflow soldering Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 Revision history . . . . . . . . . . . . . . . . . . . . . . . 42 Legal information . . . . . . . . . . . . . . . . . . . . . . 43 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Contact information . . . . . . . . . . . . . . . . . . . . 43 Contents Date of release: 10 November 2008 Document identifier: PCF8534A_3 All rights reserved. ...