ADE7752ARZ Analog Devices Inc, ADE7752ARZ Datasheet - Page 17

• Manufacturer Part Number: ADE7752ARZ
• Description: IC ENERGY METERING DETEC 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7752ARZ

• Input Impedance: 450 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 6mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER SUPPLY MONITOR
The ADE7752 contains an on-chip power supply monitor. The
power supply (V
If the supply is less than 4 V ± 5%, the outputs of the ADE7752
are inactive. This is useful to ensure correct device startup at
power-up and power-down. The power supply monitor has
built-in hysteresis and filtering. This gives a high degree of
immunity to false triggering due to noisy supplies.
As can be seen from Figure 23, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is about ±5%. The
power supply and decoupling for the part should be such that
the ripple at V
normal operation.
HPF AND OFFSET EFFECTS
Figure 25 shows the effect of offsets on the real power calcula-
tion. As can be seen, an offset on the current channel and
voltage channel contribute a dc component after multiplication.
Since this dc component is extracted by the LPF and is used to
generate the real power information for each phase, the offsets
contribute a constant error to the total real power calculation.
INTERNAL
RESET
–0.01
0.07
0.06
0.05
0.04
0.03
0.02
0.01
V
DD
0
Figure 24. Phase Error Between Channels (0 Hz to 1 kHz)
5V
4V
0V
0
INACTIVE
100
DD
Figure 23. On-Chip Power Supply Monitor
DD
does not exceed 5 V ± 5% as specified for
) is continuously monitored by the ADE7752.
200
300
ACTIVE
TIME
FREQUENCY (Hz)
400
500
600
INACTIVE
700
800
900
1000
Rev. C | Page 17 of 24
This problem is easily avoided by the HPF in the current
channels. By removing the offset from at least one channel, no
error component can be generated at dc by the multiplication.
Error terms at cos(ωt) are removed by the LPF and the digital-
to-frequency conversion. See the Digital-to-Frequency
Conversion section.
The HPFs in the current channels have an associated phase
response that is compensated for on-chip. Figure 24 and
Figure 26 show the phase error between channels with the
compensation network. The ADE7752 is phase compensated
up to 1 kHz as shown. This ensures correct active harmonic
power calculation even at low power factors.
{
V
Figure 25. Effect of Channel Offset on the Real Power Calculation
–0.002
–0.004
V
+
V
0.010
0.008
0.006
0.004
0.002
OS
V
2
×
cos
Figure 26. Phase Error Between Channels (40 Hz to 70 Hz)
× I
0
2
I
×
V × I
40
OS
2
( )
+
I
t ω
V
×
0
OS
cos
+
×
45
V
(
I
2
OS
OS
t ω
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
}
×
+
)
{
V
ω
I
50
OS
I
V
cos
FREQUENCY – RAD/S
OS
OS
FREQUENCY (Hz)
×
× V
× I
( )
I
t ω
cos
ADE7752/ADE7752A
55
+
( )
t ω
2ω
I
OS
}
+
=
60
I
OS
×
V
65
cos
( )
t ω
70