LTC4252A-2IMS Linear Technology, LTC4252A-2IMS Datasheet - Page 21

• Manufacturer Part Number: LTC4252A-2IMS
• Description: IC CTRLR HOTSWAP NEG VOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-2IMS

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Family Name: LTC4252A-2
• Package Type: MSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
As seen in Figure 6 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramatically
owing to series inductance. If this voltage avalanches the
MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB con-
nections between the sense resistor and the LTC4252’s V
and SENSE pins are strongly recommended. The drawing in
Figure 8 illustrates the correct way of making connections
between the LTC4252 and the sense resistor. PCB layout
should be balanced and symmetrical to minimize wiring
errors. In addition, the PCB layout for the sense resistor
should include good thermal management techniques for
optimal sense resistor power dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 9 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
Figure 7. Recommended Compensation
Capacitor C
60
50
40
30
20
10
0
0
IRF540S
IRF530S
2000
IRF740
C
vs MOSFET C
MOSFET C
IRF3710
4000
ISS
NTY100N10
(pF)
ISS
6000
425212 F07
8000
EE
time point 1, the supply ramps up, together with UV/OV,
V
as set by the V
exceeds V
OV < V
and TIMER < V
timing cycle starts and the TIMER capacitor is charged
by a 5.8μA current source pull-up. At time point 3, TIMER
reaches the V
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the V
tions of GATE < V
must be satisfied before a GATE ramp-up cycle begins.
SS ramps up as dictated by R
GATE is held low by the analog current limit (ACL) ampli-
fier until SS crosses 20 • V
sources into the external MOSFET gate and compensation
network. When the GATE voltage reaches the MOSFET’s
threshold, current begins flowing into the load capacitor
at time point 5. At time point 6, load current reaches the
SS control level and the analog current limit loop activates.
Between time points 6 and 8, the GATE voltage is servoed,
the SENSE voltage is regulated at V
soft-start limits the slew rate of the load current. If the
SENSE voltage (V
at time point 7, the circuit breaker TIMER activates. The
TIMER capacitor, C
current pull-up. As the load capacitor nears full charge,
load current begins to decline.
OUT
TRACK WIDTH W:
ON 1 OZ COPPER
0.03" PER AMP
Figure 8. Making PCB Connections to the Sense Resistor
and DRAIN. V
LTC4252A-1/LTC4252A-2
OVLO
LKO
CURRENT FLOW
, GATE < V
LTC4252-1/LTC4252-2
FROM LOAD
and the internal logic checks for UV > V
TMRH
IN
W
TMRL
TMRL
SENSE
GATEL
bypass capacitor. At time point 2, V
T
IN
threshold and the initial timing cycle
, is charged by a (230μA + 8 • I
. If all conditions are met, an initial
and PWRGD follow at a slower rate
GATEL
threshold is reached and the condi-
, SENSE < V
– V
SENSE
TO
SENSE RESISTOR
OS
EE
, SENSE < V
. Upon releasing GATE, 58μA
) reaches the V
SS
• C
ACL
V
TO
SS
EE
CB
(t) (Equation 7) and
and SS < 20 • V
(as in Equation 6);
CB
TO –48V BACKPLANE
CURRENT FLOW
, SS < 20 • V
CB
threshold
21
425212 F08
425212fc
UVHI
DRN
OS
OS
IN
)
,