LTC4252A-2IMS Linear Technology, LTC4252A-2IMS Datasheet - Page 28

• Manufacturer Part Number: LTC4252A-2IMS
• Description: IC CTRLR HOTSWAP NEG VOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-2IMS

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Family Name: LTC4252A-2
• Package Type: MSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
Analog Current Limit and Fast Current Limit
In Figure 17a, when SENSE exceeds V
regulated by the analog current limit amplifier loop. When
SENSE drops below V
Figure 17b, when a severe fault occurs, SENSE exceeds
V
current amplifier establishes control. If the severe fault
causes V
at V
by 8. This extra current is added to the TIMER pull-up
current of 230μA. This accelerated TIMER current of
[230μA+8 • I
delay. Careful selection of C
prevent SOA damage in a low impedance fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 180μs (or 0V to
1.4V in 230μs for the LTC4252A) at GATE start-up, as
28
FCL
DRNCL
and GATE immediately pulls down until the analog
OUT
. I
DRN
DRN
to exceed V
PWRGD
SENSE
TIMER
DRAIN
flows into the DRAIN pin and is multiplied
GATE
V
] produces a shorter circuit breaker fault
OUT
SS
DRN
ACL
1
(17a) Analog Current Limit Fault
2
DRNCL
, GATE is allowed to pull up. In
Figure 17. Current Limit Behavior (All Waveforms Are Referenced to V
3
T
4
, R
, the DRAIN pin is clamped
V
V
V
TMRH
ACL
CB
D
and MOSFET can help
5.8μA
ACL
, GATE is
5.8μA
shown in Figure 18a. If a soft-start capacitor, C
nected to this SS pin, the soft-start response is modified
from a linear ramp to an RC response (Equation 6), as
shown in Figure 18b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
time point 3 by a TIMER transition from V
(time points 1 to 2) or by the OV pin falling below the
V
is below 0.2V, the analog current limit amplifier holds
GATE low. Above 0.2V, GATE is released and 58μA ramps
up the compensation network and GATE capacitance at
time point 4. Meanwhile, the SS pin voltage continues to
ramp up. When GATE reaches the MOSFET’s threshold,
the MOSFET begins to conduct. Due to the MOSFET’s high
g
control value of V
GATE voltage is controlled by the current limit amplifier.
The soft-start control voltage reaches the circuit breaker
voltage, V
activates. As the load capacitor nears full charge, load
m
OVLO
, the MOSFET current quickly reaches the soft-start
PWRGD
SENSE
TIMER
DRAIN
GATE
V
OUT
threshold after an OV condition. When the SS pin
V
SS
V
DRNCL
DRN
TMRH
CB
, at time point 7 and the circuit breaker TIMER
1
V
(17b) Fast Current Limit Fault
FCL
CB TIMES OUT
ACL
2
V
(t) (Equation 7). At time point 6, the
ACL
V
CB
EE
)
425212 F17
TMRH
SS
to V
, is con-
425212fc
TMRL