LTC4252A-2IMS Linear Technology, LTC4252A-2IMS Datasheet - Page 9

• Manufacturer Part Number: LTC4252A-2IMS
• Description: IC CTRLR HOTSWAP NEG VOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-2IMS

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Family Name: LTC4252A-2
• Package Type: MSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TYPICAL PERFORMANCE CHARACTERISTICS
PIN FUNCTIONS
V
pin to the positive side of the supply through a dropping
resistor. A shunt regulator clamps V
undervoltage lockout (UVLO) circuit holds GATE low until
the V
UV is high, OV is low and V
starts an initial timing cycle before initiating a GATE ramp-
up. If V
immediately.
PWRGD (Pin 2/Not Available): Power Good Status Output
(MS only). At start-up, PWRGD latches low if DRAIN is
below 2.385V and GATE is within 2.8V of V
status is reset by UV, V
timeout. This pin is internally pulled high by a 58μA cur-
rent source.
SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the sense
resistor during the soft-start current limiting. At the begin-
ning of a start-up cycle, the SS capacitor (C
by a 22μA (28μA for the LTC4252A) current source. The
IN
62
61
60
59
58
57
56
55
(Pin 1/Pin 1): Positive Supply Input. Connect this
IN
–55 –35 –15
I
IN
PGH
V
(MS ONLY)
pin is greater than V
PWRGD
drops below approximately 8.2V, GATE pulls low
vs Temperature
= 0V
TEMPERATURE (°C)
5
25
45
IN
(UVLO) or a circuit breaker fault
65
IN
(MS/MS8)
LKO
85 105 125
comes out of UVLO, TIMER
, overriding UV and OV. If
425212 G38
IN
at 13V. An internal
SS
220
210
200
190
180
170
160
150
IN
–55 –35 –15
) is ramped
t
. PWRGD
SS
SS PIN FLOATING,
V
SS
vs Temperature
RAMPS FROM 0.2V TO 2V
TEMPERATURE (°C)
5
25
GATE pin is held low until SS exceeds 20 • V
SS is internally shunted by a 100k resistor (R
limits the SS pin voltage to 2.2V (50k resistor and 1.4V
for the LTC4252A). This corresponds to an analog current
limit SENSE voltage of 100mV (60mV for the LTC4252A). If
the SS capacitor is omitted, the SS pin ramps up in about
180μs. The SS pin is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor R
nected between SENSE and V
steps. If SENSE exceeds V
comparator activates a (230μA + 8 • I
current. If SENSE exceeds V
amplifier pulls GATE down to regulate the MOSFET current
at V
SENSE may overshoot. If SENSE reaches V
the fast current limit comparator pulls GATE low with a
strong pull-down. To disable the circuit breaker and cur-
rent limit functions, connect SENSE to V
45
ACL
65
LTC4252A-1/LTC4252A-2
/R
85 105 125
S
. In the event of a catastrophic short-circuit,
425212 G27
LTC4252-1/LTC4252-2
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–55
t
vs Temperature
PLLUG
CB
t
PLLUG
–35
ACL
(50mV), the circuit breaker
EE
t
PHLOG
–15
and t
, the analog current limit
, and controlled in three
TEMPERATURE (°C)
5
PHLOG
DRN
25
EE
) TIMER pull-up
45
.
FCL
65
OS
SS
(200mV),
85 105
) which
= 0.2V.
S
425212 G24
425212fc
con-
9
125