ISL6209CBZ Intersil, ISL6209CBZ Datasheet - Page 5

• Manufacturer Part Number: ISL6209CBZ
• Description: IC MOSFET DRVR SYNC BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6209CBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 33V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
NOTE:
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller. In
addition, place a 500kΩ resistor to ground from this pin. This
allows for proper three-state operation under all start-up
conditions.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin. All signals are referenced to this
node.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
LGATE Turn-On Propagation Delay
OUTPUT
Upper Drive Source Resistance
Upper Driver Source Current (Note 5)
Upper Drive Sink Resistance
Upper Driver Sink Current (Note 5)
Lower Drive Source Resistance
Lower Driver Source Current (Note 5)
Lower Drive Sink Resistance
Lower Driver Sink Current (Note 5)
5. Guaranteed by characterization, not 100% tested in production.
PARAMETER
5
Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
t
PDHLGATE
SYMBOL
R
R
R
R
I
I
I
I
UGATE
UGATE
LGATE
LGATE
UGATE
UGATE
LGATE
LGATE
V
DELAY = VCC
500mA Source Current
V
500mA Sink Current
V
500mA Source Current
V
500mA Sink Current
V
VCC
UGATE-PHASE
UGATE-PHASE
LGATE
LGATE
ISL6209
= 5V, Outputs Unloaded,
= 2.5V
= 2.5V
TEST CONDITIONS
DELAY (Pin 7 for SOIC-8, Pin 6 for QFN)
The DELAY pin sets the dead-time between gate switching
for the ISL6209. Connect a resistor to GND from this pin to
adjust the dead-time, refer to Figure 4. Tie this pin to VCC to
disable the delay circuitry. See Shoot-Through Protection
section for more detail.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
Description
Operation
Designed for speed, the ISL6209 dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one
externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
times [t
section. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[t
drops below 1V. This prevents both the lower and upper
MOSFETs from conducting simultaneously, or shoot-
through. Once this delay period is completed, the upper gate
drive begins to rise [t
turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
upper gate begins to fall [t
= 2.5V
= 2.5V
PDHUGATE
PDLLGATE
FLGATE
], based on how quickly the LGATE voltage
] are provided in the Electrical Specifications
], the lower gate begins to fall. Typical fall
PDLUGATE
RUGATE
FUGATE
MIN
10
], and the upper MOSFET
-
-
-
-
-
-
-
-
] is encountered before the
]. Again, the adaptive
TYP
1.0
2.0
1.0
2.0
1.0
2.0
0.4
4.0
20
MAX
2.5
2.5
2.5
1.0
30
-
-
-
-
UNITS
ns
Ω
A
Ω
A
Ω
A
Ω
A