ISL6209CBZ Intersil, ISL6209CBZ Datasheet - Page 7

• Manufacturer Part Number: ISL6209CBZ
• Description: IC MOSFET DRVR SYNC BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6209CBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 33V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The equation governing the dead-time seen in Figure 4 is
expressed as:
The equation can be rewritten to solve for R
follows:
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage
rating above the maximum battery voltage plus 5V. The
bootstrap capacitor can be chosen from the following
equation:
where Q
charge the gate of the upper MOSFET. The ΔV
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125μF is required.
The next larger standard value capacitance is 0.22μF. A
good quality ceramic capacitor is recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
T
R
C
DELAY
DELAY
BOOT
FIGURE 5. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
≥
0.0
GATE
=
=
----------------------- -
ΔV
GATE
20nC
Q
[
(
------------------------------------------- -
(
GATE
T
BOOT
160
160
0.1
DELAY
VOLTAGE
is the amount of gate charge required to fully
, of 25nC at 5V and also assume the droop in
×
×
10
0.2
10
Q
–
GATE
–
–
15
6ns
15
0.3
)
= 100nC
×
)
R
ΔV
0.4
DELAY
BOOT_CAP
7
0.5
]
+
6ns
0.6
(V)
0.7
DELAY
BOOT
0.8
as
0.9
term is
1.0
ISL6209
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
P
where f
and V
and Q
MOSFET selection and any external capacitance added to
the gate pins. The I
of the driver and is typically negligible.
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices
(both upper and lower FETs) could cause increased PHASE
ringing, which may lead to voltages that exceed the absolute
maximum rating of the devices. When PHASE rings below
ground, the negative voltage could add charge to the
bootstrap capacitor through the internal bootstrap diode.
Under worst-case conditions, the added charge could
overstress the BOOT and/or PHASE pins. To prevent this
from happening, the user should perform a careful layout
inspection to reduce trace inductances, and select low lead
inductance MOSFETs and drivers. D
packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must
be used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
=
1000
900
800
700
600
500
400
300
200
100
f
sw
0
FIGURE 6. POWER DISSIPATION vs FREQUENCY
L
L
0
sw
(
Q
Q
represent the upper and lower gate rail voltage. Q
is the upper and lower gate charge determined by
1.5V
U
L
is the switching frequency of the PWM signal. V
= 200nC
200
=100nC
U
Q
U
400
+
V
VCC
L
600
Q
Q
Q
L
U
L
V
)
FREQUENCY (kHz)
= 100nC
CC
+
=50nC
800 1000 1200
I
VCC
product is the quiescent power
V
CC
2
PAK and DPAK
1400
1600
Q
Q
Q
Q
U
L
U
L
= 50nC
= 50nC
= 20nC
= 50nC
1800 2000
U
U