L6599ADTR STMicroelectronics, L6599ADTR Datasheet - Page 7

• Manufacturer Part Number: L6599ADTR
• Description: IC RESONANT CONVRTR CTRLR 16SOIC
• Manufacturer: STMicroelectronics

Specifications of L6599ADTR

• Applications: Resonant Converter Controller
• Voltage - Supply: 8.85 V ~ 16 V
• Current - Supply: 3.5mA
• Operating Temperature: 0°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Operating Supply Voltage: 8.15 V, 10.7 V, 17 V
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• For Use With: 497-10542 - BOARD EVAL BASED ON L6599497-8429 - BOARD ADAPTER L6599/STP12NM50N497-5496 - EVAL BOARD FOR L6599
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 497-8519-2

L6599A
Table 2.
Pin N#
10
11
12
13
14
15
16
9
PFC_STOP
Pin description (continued)
VBOOT
Type
GND
OUT
HVG
N.C.
LVG
Vcc
Open-drain ON/OFF control of PFC controller. This pin, normally open, is
intended for stopping the PFC controller, for protection purpose or during
burst-mode operation. It goes low when the IC is shut down by DIS>1.85 V,
ISEN > 1.5 V, LINE > 6 V and STBY < 1.24 V. The pin is pulled low also
when the voltage on pin DELAY exceeds 2 V and goes back open as the
voltage falls below 0.3 V. During UVLO, it is open. Leave the pin
unconnected if not used.
Chip ground. Current return for both the low-side gate-drive current and
the bias current of the IC. All of the ground connections of the bias
components should be tied to a track going to this pin and kept separate
from any pulsed current return.
Low-side gate-drive output. The driver is capable of 0.3 A min. source and
0.8 A min. sink peak current to drive the lower MOSFET of the half-bridge
leg. The pin is actively pulled to GND during UVLO.
Supply voltage of both the signal part of the IC and the low-side gate
driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be
useful to get a clean bias voltage for the signal part of the IC.
High-voltage spacer. The pin is not internally connected to isolate the high-
voltage pin and ease compliance with safety regulations (creepage
distance) on the PCB.
High-side gate-drive floating ground. Current return for the high-side gate-
drive current. Layout carefully the connection of this pin to avoid too large
spikes below ground.
High-side floating gate-drive output. The driver is capable of 0.3 A min.
source and 0.8 A min. sink peak current to drive the upper MOSFET of the
half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures
that the pin is not floating during UVLO.
High-side gate-drive floating supply Voltage. The bootstrap capacitor
connected between this pin and pin 14 (OUT) is fed by an internal
synchronous bootstrap diode driven in-phase with the low-side gate-drive.
This patented structure replaces the normally used external diode.
Doc ID 15308 Rev 5
Function
Pin connection
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