MAX16065ETM+ Maxim Integrated Products, MAX16065ETM+ Datasheet - Page 43

• Manufacturer Part Number: MAX16065ETM+
• Description: IC SYSTEM MANAGER 12CH 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16065ETM+

• Applications: Power Supply Monitor, Sequencer
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Number Of Voltages Monitored: 12
• Undervoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 us
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Maximum Power Dissipation: 2222 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

page is currently selected. The write byte procedure is
the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a write
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends an 8-bit data byte.
7) The addressed slave asserts an ACK on SDA.
8) The master sends a STOP condition.
To write a single byte, only the 8-bit memory address
and a single 8-bit data byte are sent. The data byte is
written to the addressed location if the memory address
is valid. The slave asserts a NACK at step 5 if the mem-
ory address is not valid.
When PEC is enabled, the Write Byte protocol becomes:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write
3) The addressed slave asserts an ACK on the data line.
4) The master sends an 8-bit memory address.
5) The active slave asserts an ACK on the data line.
6) The master sends an 8-bit data byte.
7) The slave asserts an ACK on the data line.
8) The master sends an 8-bit PEC byte.
9) The slave asserts an ACK on the data line (if PEC is
10) The master generates a STOP condition.
The read byte protocol (see Figure 14) allows the master
device to read a single byte located in the default page,
extended page, or flash page depending on which page
is currently selected. The read byte procedure is the
following:
1)
2)
3)
4)
12-Channel/8-Channel, Flash-Configurable System
bit (low).
bit (low).
good, otherwise NACK).
The master sends a START condition.
The master sends the 7-bit slave address and a
write bit (low).
The addressed slave asserts an ACK on SDA.
The master sends an 8-bit memory address.
Managers with Nonvolatile Fault Registers
______________________________________________________________________________________
Read Byte
5)
6)
7)
8)
9)
10) The master asserts a NACK on SDA.
11) The master sends a STOP condition.
If the memory address is not valid, it is NACKed by the
slave at step 5 and the address pointer is not modified.
When PEC is enabled, the Read Byte protocol becomes:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write
3) The addressed slave asserts an ACK on the data line.
4) The master sends 8-bit memory address.
5) The active slave asserts an ACK on the data line.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave ID plus a read
8) The addressed slave asserts an ACK on the data line.
9) The slave sends 8 data bits.
10) The master asserts an ACK on the data line.
11) The slave sends an 8-bit PEC byte.
12) The master asserts a NACK on the data line.
13) The master generates a STOP condition.
The block write protocol (see Figure 14) allows the mas-
ter device to write a block of data (1 byte to 16 bytes) to
memory. Preload the destination address by a previous
send byte command; otherwise the block write com-
mand begins to write at the current address pointer.
After the last byte is written, the address pointer remains
preset to the next valid address. If the number of bytes
to be written causes the address pointer to exceed 8Fh
for configuration registers or configuration flash or FFh
for user flash, the address pointer stays at 8Fh or FFh,
respectively, overwriting this memory address with the
remaining bytes of data. The slave generates a NACK at
step 5 if the command code is invalid or if the device is
busy, and the address pointer is not altered.
bit (low).
bit (high).
The addressed slave asserts an ACK on SDA.
The master sends a REPEATED START condition.
The master sends the 7-bit slave address and a
read bit (high).
The addressed slave asserts an ACK on SDA.
The slave sends an 8-bit data byte.
Block Write
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