AD637JQ Analog Devices Inc, AD637JQ Datasheet - Page 10

IC RMS/DC CONV PRECISION 14-CDIP

AD637JQ

Manufacturer Part Number
AD637JQ
Description
IC RMS/DC CONV PRECISION 14-CDIP
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD637JQ

Rohs Status
RoHS non-compliant
Current - Supply
2.2mA
Voltage - Supply
±3.0V ~ 18V
Mounting Type
Through Hole
Package / Case
14-CDIP (0.300", 7.62mm)
Accuracy %
0.25%
Bandwidth
200kHz
Supply Current
2.2mA
Power Dissipation Pd
108mW
Supply Voltage Range
± 3V To ± 18V
Digital Ic Case Style
DIP
No. Of Pins
14
Input Type
RMS
Module Type
Converter
Output Type
DC
Voltage, Supply
± 18 VDC
For Use With
AD637-EVALZ - BOARD EVALUATION FOR AD637
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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+
Figure 12 shows values of C
error as a function of sine wave frequency for the standard rms
connection. The 1% settling time is shown on the right side of
Figure 12.
Figure 13 shows the relationship between the averaging error,
signal frequency settling time, and averaging capacitor value.
Figure 13 is drawn for filter capacitor values of 3.3× the
averaging capacitor value. This ratio sets the magnitude of the
ac and dc errors equal at 50 Hz. As an example, by using a 1 μF
averaging capacitor and a 3.3 μF filter capacitor, the ripple for
a 60 Hz input signal is reduced from 5.3% of the reading using
the averaging capacitor alone to 0.15% using the 1-pole filter.
This gives a factor of 30 reduction in ripple, and yet the settling
time only increases by a factor of 3. The values of filter
Capacitor C
the desired value of averaging error and settling time by using
Figure 13.
The symmetry of the input signal also has an effect on the
magnitude of the averaging error. Table 5 gives the practical
component values for various types of 60 Hz input signals.
These capacitor values can be directly scaled for frequencies
other than 60 Hz—that is, for 30 Hz, these values are doubled,
and for 120 Hz they are halved.
For applications that are extremely sensitive to ripple, the 2-pole
configuration is suggested. This configuration minimizes capacitor
values and the settling time while maximizing performance.
Figure 14 can be used to determine the required value of C
C2, and C3 for the desired level of ripple and settling time.
AD637
+V
C2
S
4.7kΩ
1
2 NC
3 COMMON
4
5
6
7
AV
BUFF IN
OUTPUT
OFFSET
CS
DEN
INPUT
dB OUTPUT
and Filter Capacitor C2 can be calculated for
25kΩ
Figure 11. 2-Pole Sallen-Key Filter
BIAS
AV
SQUARER/
AD637
and the corresponding averaging
DIVIDER
24kΩ
RX
ABSOLUTE
VALUE
25kΩ
BUFF
FOR A SINGLE-POLE
OUT
+V
C
–V
V
FILTER SHORT RX
NC
AND REMOVE C3
AV
IN
S
S
14
13
12
11
10
9
8
+
24kΩ
C
AV
RMS OUT
+V
–V
V
IN
S
S
+
AV
C3
Rev. K | Page 10 of 20
,
Figure 12. Values for C
Figure 13. Values of C
Figure 14. Values of C
0.01
100
Reading Averaging Error* for 2-Pole Sallen-Key Filter (see * in Figure)
1.0
0.1
0.01
0.01
10
100
100
0.1
0.1
Error* Accuracy Includes ±2% Component Tolerance (see * in Figure)
10
10
1
1
1
1
1
*%dc ERROR + %RIPPLE (PEAK)
*%dc ERROR + %RIPPLE (PEAK)
ACCURACY ±20% DUE TO
COMPONENT TOLERANCE
Averaging Error* for 1-Pole Post Filter (see * in Figure)
10
10
10
AV
AV
and 1% Settling Time for Stated % of Reading Averaging
AV
, C2, and 1% Settling Time for Stated % of Reading
INPUT FREQUENCY (Hz)
, C2, and C3 and 1% Settling Time for Stated % of
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
100
100
100
*%dc ERROR + %RIPPLE (PEAK)
ACCURACY ±20% DUE TO
COMPONENT TOLERANCE
1k
1k
1k
10k
10k
10k
100k
1
100k
00k
100
10
1.0
0.1
0.01
100
10
1
0.1
0.01
100
10
1
0.1
0.01

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