STTS75DS2F STMicroelectronics, STTS75DS2F Datasheet - Page 21

• Manufacturer Part Number: STTS75DS2F
• Description: IC TEMP SENSOR DGTL WCHDG 8MSOP
• Manufacturer: STMicroelectronics

Specifications of STTS75DS2F

• Function: Temp Sensor, Watchdog
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -55°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Full Temp Accuracy: +/- 3 C
• Digital Output - Bus Interface: Serial (2-Wire, I2C)
• Digital Output - Number Of Bits: 12 bit
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• For Use With: 497-8844 - EVAL DAUGHTER STTS75 8-TSSOP497-8419 - BOARD ST72651AR6/STTS75/STLM20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6331-2

STTS75
3.3
Note:
3.4
3.4.1
3.4.2
3.4.3
Serial interface
Writing to and reading from the STTS75 registers is accomplished via the two-wire serial
interface protocol which requires that one device on the bus initiates and controls all READ
and WRITE operations. This device is called the “master” device. The master device also
generates the SCL signal which provides the clock signal for all other devices on the bus.
These other devices on the bus are called “slave” devices. The STTS75 is a slave device
(see
During operations, one data bit is transmitted per clock cycle. All operations follow a
repeating, nine-clock-cycle pattern that consists of eight bits (one byte) of transmitted data
followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device.
There are no unused clock cycles during any operation, so there must not be any breaks in
the data stream and ACKs/NACKs during data transfers. Conversely, having too few clock
cycles can lead to incorrect operation if an inadvertent 8-bit READ from a 16-bit register
occurs.
Table 11.
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
●
●
●
●
Accordingly, the following bus conditions have been defined (see
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
MSB
Bit7
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Table
1
11). Both the master and slave devices can send and receive data on the bus.
STTS75 serial bus slave addresses
Bit6
0
Bit5
0
Doc ID 13298 Rev 11
Bit4
1
Bit3
A2
Bit2
A1
Figure 6 on page
Functional description
Bit1
A0
22):
R/W
Bit0
LSB
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