ISL6269BCRZ Intersil, ISL6269BCRZ Datasheet - Page 8

• Manufacturer Part Number: ISL6269BCRZ
• Description: IC PWM CTRLR SYNC BUCK 16-QFN
• Manufacturer: Intersil

Specifications of ISL6269BCRZ

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 600kHz
• Voltage - Supply: 5 V ~ 25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Frequency-max: 600kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -

The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if
POR threshold
threshold
identification capability that can drastically reduce trouble-
shooting time and effort. The pull-down resistance of the
PGOOD pin corresponds to the fault status of the controller.
During soft-start or if an undervoltage fault occurs, the
PGOOD pulldown resistance is 95Ω, or 30Ω for an
overcurrent fault, or 60Ω for an overvoltage fault.
MOSFET Gate-Drive Outputs LG and UG
The ISL6269B has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The LG gate-driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant, requiring a low
r
order to clamp the gate of the MOSFET below the V
turnoff. The current transient through the gate at turnoff can
be considerable because the switching charge of a low
r
protection prevents a gate-driver output from turning on until
the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 5 is
extended by the additional period that the falling gate voltage
stays above the 1V threshold. The high-side gate-driver
output voltage is measured across the UG and PHASE pins
while the low-side gate-driver output voltage is measured
across the LG and PGND pins. The power for the LG
gate-driver is sourced directly from the PVCC pin. The power
DS(ON)
DS(ON)
Soft Start or Undervoltage
VCC Below POR
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
MOSFET. The LG pulldown resistance is small in
MOSFET can be large. Adaptive shoot-through
Overvoltage
Overcurrent
V
VCC_THF
FIGURE 4. SOFT-START SEQUENCE
1.5ms
V
VCC_THR
. The ISL6269B features a unique fault-
VCC and PVCC
V
, or if
VCC
PGOOD
2.75ms
VOUT
EN
has not reached the rising
8
V
VCC
PGOOD RESISTANCE
is below the falling POR
Undefined
95Ω
60Ω
30Ω
GS(th)
at
ISL6269B
for the UG gate-driver is sourced from a “boot” capacitor
connected across the BOOT and PHASE pins. The boot
capacitor is charged from a 5V bias supply through a “boot
diode” each time the low-side MOSFET turns on, pulling the
PHASE pin low. The ISL6269B has an integrated boot diode
connected from the PVCC pin to the BOOT pin.
Diode Emulation
The ISL6269B normally operates in continuous-conduction-
mode (CCM), minimizing conduction losses by forcing the
low-side MOSFET to operate as a synchronous rectifier. An
improvement in light-load efficiency is achieved by allowing
the converter to operate in diode-emulation-mode (DEM),
where the low-side MOSFET behaves as a smart-diode,
forcing the device to block negative inductor current flow.
The ISL6269B can be configured to operate in DEM by
setting the FCCM pin low. Setting the FCCM pin high will
disable DEM.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current usually flows into
the drain of the low-side MOSFET. When the low-side
MOSFET conducts positive inductor current, the phase
voltage will be negative with respect to the GND and PGND
pins. Conversely, when the low-side MOSFET conducts
negative inductor current, the phase voltage will be positive
with respect to the GND and PGND pins. Negative inductor
current occurs when the output load current is less than ½
the inductor ripple current. Sinking negative inductor current
through the low-side MOSFET lowers efficiency through
unnecessary conduction losses. Efficiency can be further
improved with a reduction of unnecessary switching losses
by reducing the PWM frequency. It is characteristic of the R
architecture for the PWM frequency to decrease while in
diode emulation. The extent of the frequency reduction is
proportional to the reduction of load current. Upon entering
DEM, the PWM frequency makes an initial step-reduction
because of a 33% step-increase of the window voltage V
The ISL6269B features an audio filter that clamps the
UG
LG
t
LGFUGR
FIGURE 5. LG AND UG DEAD-TIME
50%
50%
t
UGFLGR
May 30, 2007
FN6280.2
W
3
.