LNBH24LQTR STMicroelectronics, LNBH24LQTR Datasheet - Page 13

• Manufacturer Part Number: LNBH24LQTR
• Description: IC LNBS DUAL SUPPLY/CTRL 32-QFN
• Manufacturer: STMicroelectronics

Specifications of LNBH24LQTR

• Applications: Converter, Analog and Digital Satellite STB Receivers/SatTV
• Voltage - Input: 8 ~ 15 V
• Number Of Outputs: 2
• Voltage - Output: 13.3V, 18.2V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10615-2

LNBH24L
6
6.1
6.2
6.3
6.4
6.5
I²C bus interface
Data transmission from main microprocessor to the LNBH24L and vice versa takes place
through the 2 wires I²C bus interface, consisting of the 2 lines SDA and SCL (pull-up
resistors to positive supply voltage must be externally connected).
Data validity
As shown in
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
Start and stop condition
As shown in
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see
to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate acknowledge after the reception of each byte, otherwise the SDA line remain at the
HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH24L won't generate
acknowledge if the V
Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH24L, the microprocessor can use a simpler
transmission: simply it waits one clock without checking the slave acknowledging, and sends
the new data. This approach of course is less protected from misworking and decreases the
noise immunity.
Figure 6
Figure 7
CC
, the data on the SDA line must be stable during the high semi-period
a start condition is a HIGH to LOW transition of the SDA line while
supply is below the under-voltage lockout threshold (6.7 V typ.).
Doc ID 16857 Rev 2
Figure 8
). The peripheral (LNBH24L) that acknowledges has
I²C bus interface
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