ISL6312CRZ-T Intersil, ISL6312CRZ-T Datasheet - Page 23

• Manufacturer Part Number: ISL6312CRZ-T
• Description: IC CTRLR PWM 4PHASE BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6312CRZ-T

• Applications: Controller, Intel VR10, VR11, AMD CPU
• Voltage - Input: 5 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.38 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TD1 is a fixed delay with the typical value as 1.40ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
During TD2 and TD4, ISL6312 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R
second soft-start ramp time TD2 and TD4 can be calculated
based on Equations 18 and 19:
For example, when VID is set to 1.5V and the R
100kΩ, the first soft-start ramp time TD2 will be 704µs and
the second soft-start ramp time TD4 will be 256µs.
NOTE: If the SS pin is grounded, the soft-start ramp in TD2
and TD4 will be defaulted to a 6.25mV step frequency of
330kHz.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TD5. The typical value
for TD5 is 440µs.
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of three periods, as shown
in Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period TDA. After this delay period the ISL6312 will
begin ramping the output voltage to the desired DAC level at
a fixed rate of 6.25mV per step, with a stepping frequency of
330kHz. The amount of time required to ramp the output
voltage to the final DAC voltage is referred to as TDB, and
can be calculated as shown in Equation 20:
TD2
TD4
=
=
1.1 R
------------------------ μs
--------------------------------------------------- - μs
6.25 25
(
V
VID
⋅
FIGURE 11. SOFT-START WAVEFORMS
⋅
6.25 25
SS
–
VOUT, 500mV/DIV
1.1
(
TD1
⋅
) R
)
⋅
PGOOD
EN_VTT
SS
(
TD2
SS
500µs/DIV
)
23
from SS pin to GND. The
TD3 TD4
TD5
SS
is set at
(EQ. 18)
(EQ. 19)
ISL6312
.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TDC. The typical value
for TDC can range between 1.5ms and 3.0ms.
Pre-Biased Soft-Start
The ISL6312 also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
TDB
GND>
GND>
FIGURE 13. SOFT-START WAVEFORMS FOR ISL6312-BASED
=
OUTPUT PRECHARGED
------------------------- -
330
BELOW DAC LEVEL
FIGURE 12. SOFT-START WAVEFORMS
1
×
OUTPUT PRECHARGED
10
MULTIPHASE CONVERTER
ABOVE DAC LEVEL
TDA
VOUT, 500mV/DIV
3
⋅
T1
⎛
⎝
-------------------- -
0.00625
T2
V
PGOOD
EN_VTT
VID
⎞
⎠
500µs/DIV
TDB
T3
TDC
V
OUT
EN (5V/DIV)
(0.5V/DIV)
February 1, 2011
(EQ. 20)
FN9289.6