MAX8770GTL+T Maxim Integrated Products, MAX8770GTL+T Datasheet - Page 14

• Manufacturer Part Number: MAX8770GTL+T
• Description: IC CTLR PS 2/1PH QUICK PWM 40QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8770GTL+T

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4 ~ 26 V
• Number Of Outputs: 1
• Voltage - Output: 0.125 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWM Controller for IMVP-6+ CPU Core Power Supplies
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL
14
PIN
1
2
3
4
5
6
7
8
9
______________________________________________________________________________________
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
PWRGD
VRHOT
CLKEN
NAME
POUT
THRM
TIME
TON
CCV
PSI
Clock-Enable Logic Output. This inverted logic output indicates when the output voltage sensed at FB is in
regulation. CLKEN is forced low during VID transitions. Except during startup, CLKEN is the inverse of
PWRGD. See the Startup Timing Diagram (Figure 9). When in pulse-skipping mode (DPRSLPVR high), the
upper CLKEN threshold is disabled.
Open-Drain, Power-Good Output. After output-voltage transitions, except during power-up and power-
down, if FB is in regulation then PWRGD is high impedance. During startup, PWRGD is held low and
continues to be low while the part is in boot mode and until 5ms (typ) after CLKEN goes low.
PWRGD is forced low in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is
active (output-voltage transitions).
When in pulse-skipping mode (DPRSLPVR high), the upper PWRGD threshold comparator is blanked.
A pullup resistor on PWRGD causes additional finite shutdown current.
Logic Input to Indicate Power Usage. PSI and DPRSLPVR together determine the operating mode as
shown in the truth table below. Blank the PWRGD upper threshold when the part is in skip mode. The part
is forced into full-phase PWM mode during startup, while in boot mode, during the transition from
boot mode to VID mode and during shutdown:
DPRSLPVR
Power-Monitor Output: V
monitor scale factor:
CSNpm = CSN12 for MAX8771.
CSNpm = CSN2 for MAX8770/MAX8772.
POUT is zero in shutdown.
Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below
1.5V (30% of V
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V
GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of V
desired high temperature.
Slew-Rate Adjustment Pin. Connect a resistor R
where R
This slew rate applies to transitions into and out of the low-power pulse-skipping modes (and to the
transition from boot mode to VID mode. The slew rate for startup and shutdown is 1/8 this value. If the VID
DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are
clocked, up to a maximum slew rate equal to the one set by R
Switching-Frequency Setting Input. An external resistor between the input power source and TON sets the
switching period (T
where C
TON is high impedance in shutdown.
Integrator Capacitor Connection. Connect a 470pF x (2/η
to set the integration time constant. The integrator is internally disabled when the part is in skip mode and
the output is above regulation.
1
1
0
0
TIME
TON
= 16.26pF.
is between 35.7kΩ and 178kΩ.
PSI
CC
0
1
0
1
). VRHOT is high impedance in shutdown.
SW
Mode
Very low current (1-phase skip)
Low current (approximately 3A) (1-phase skip)
Intermediate power potential (1-phase PWM)
Max power potential (2- or 1-phase PWM as configured at CSP2)
= 1/f
POUT
SW
) per phase according to the following equation:
= K
Slew rate = (12.5mV/µs) x (71.5kΩ_/ R
PWR
x V(CSNpm, GNDS) x ΣV(CSP_, CSN_), where K
T
SW
= C
TIME
FUNCTION
TON
from TIME to GND to set the internal slew rate:
(R
TON
TOTAL
+ 6.5kΩ)
TIME
) x 300kHz/f
as defined above.
®
TIME
IMVP-6 LICENSEES
)
SW
capacitor from CCV to GND
Pin Description
PWR
is the power
CC
CC
) at the
and